1-2hit |
Graphene has been expected as an alternative material for copper interconnects in which resistance increases and reliability deteriorates in nanoscale. While the principle advantages are verified by simulations and experiments, they have not been put into practical use due to the immaturity of the manufacturing process leading to mass production. On the other hand, recent steady progress in the fabrication process has increased the possibility of practical application. In this paper, I will review the recent advances and the latest prospects for conductor applications of graphene centered on interconnects. The possibility of further application utilizing the unique characteristics of graphene is discussed.
Noriaki ODA Hironori IMURA Naoyoshi KAWAHARA Masayoshi TAGAMI Hiroyuki KUNISHIMA Shuji SONE Sadayuki OHNISHI Kenta YAMADA Yumi KAKUHARA Makoto SEKINE Yoshihiro HAYASHI Kazuyoshi UENO
A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.