IEICE TRANSACTIONS on Electronics
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation
Summary :
A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.848-855
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.848
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
- Device
Authors
Noriaki ODA
Hironori IMURA
Naoyoshi KAWAHARA
Masayoshi TAGAMI
Hiroyuki KUNISHIMA
Shuji SONE
Sadayuki OHNISHI
Kenta YAMADA
Yumi KAKUHARA
Makoto SEKINE
Yoshihiro HAYASHI
Kazuyoshi UENO
Keyword
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Noriaki ODA, Hironori IMURA, Naoyoshi KAWAHARA, Masayoshi TAGAMI, Hiroyuki KUNISHIMA, Shuji SONE, Sadayuki OHNISHI, Kenta YAMADA, Yumi KAKUHARA, Makoto SEKINE, Yoshihiro HAYASHI, Kazuyoshi UENO, "Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 848-855, April 2007, doi: 10.1093/ietele/e90-c.4.848.
Abstract: A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.848/_p
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@ARTICLE{e90-c_4_848,
author={Noriaki ODA, Hironori IMURA, Naoyoshi KAWAHARA, Masayoshi TAGAMI, Hiroyuki KUNISHIMA, Shuji SONE, Sadayuki OHNISHI, Kenta YAMADA, Yumi KAKUHARA, Makoto SEKINE, Yoshihiro HAYASHI, Kazuyoshi UENO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation},
year={2007},
volume={E90-C},
number={4},
pages={848-855},
abstract={A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.},
keywords={},
doi={10.1093/ietele/e90-c.4.848},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation
T2 - IEICE TRANSACTIONS on Electronics
SP - 848
EP - 855
AU - Noriaki ODA
AU - Hironori IMURA
AU - Naoyoshi KAWAHARA
AU - Masayoshi TAGAMI
AU - Hiroyuki KUNISHIMA
AU - Shuji SONE
AU - Sadayuki OHNISHI
AU - Kenta YAMADA
AU - Yumi KAKUHARA
AU - Makoto SEKINE
AU - Yoshihiro HAYASHI
AU - Kazuyoshi UENO
PY - 2007
DO - 10.1093/ietele/e90-c.4.848
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.
ER -
English
