A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.

A 7-mask self-aligned SiGe base bipolar transistor has been newly developed. This transistor offers several advancements to a super self-aligned selectively grown SiGe base (SSSB) transistor which has a selectively grown SiGe-base layer formed by a cold-wall ultra high vacuum (UHV)/CVD system. The advancements are as follows: (1) a BPSG-filled arbitrarywidth trench isolation on a SOI is formed by a high-uniformity CMP with a hydro-chuck for reducing the number of isolation fabrication steps, (2) polysilicon-plug emitter and collector electrodes are made simultaneously using an in-situ phosphorusdoped polysilicon film to decrease the distance between emitter and collector electrodes and also to reduce the fabrication steps of the elecrodes, (3) a n+-buried collector layer is made by a high-energy phosphorus ion-implantation technique to eliminate collector epitaxial growth, and (4) a germanium profile in the neutral base region is optimized to increase the fT value without increasing leakage current at the base-cellector junction. In the developed transistor, a high performance of 80-GHz fT and mask-steps reduction are simultaneously achieved.

This paper presents a design for a 1.55 µm, 450 Mbit/s high-sensitivity receiver, employing an InGaAs/InGaAsP/InP-APD and a high-impedance preamplifier with a GaAs MESFET front-end circuit. Studying Ge-APDs and InGaAs/InGaAsP/InP-APDs, it is confirmed that InGaAs/InGaAsP/InP-APDs are suitable for the wavelength region around 1.55 µm and transmission bit rates near 450 Mbit/s. Further studies on InGaAs/InGaAsP/InP-APDs confirm that they should be used in the lower multiplication reqion: e.g. less than 15. Using a InGaAs/InGaAsP/InP-APD and a high-impedance preamplifier, a receiver sensitivity of -42.9 dBm at a bit error rate of 10-11 is realized. Applying this receiver with a high power optical source, a stable longitudinal spectrum distributed feedback laser diode (DFB-LD), a 450 Mbit/s transmission experiment over 210 km distance is successfully carried out.