A millimeter-wave radar receiver using a z-cut LiNbO3 optical modulator with orthogonal-gap-embedded patch-antennas on a low-k dielectric material is proposed. A millimeter-wave from a reflected radar signal can be received by the patch-antennas and converted directly to a lightwave through electro-optic modulation. A low-k dielectric material is used as a substrate for improving antenna gain. Additionally, an interaction length between millimeter-wave and lightwave electric fields becomes long. As a result, large modulation efficiency can be obtained, which is proportional to sensitivity of the millimeter-wave radar receiver. Optical millimeter-wave radar beam-forming can be obtained using the proposed device with meandering-gaps for controlling interaction between millimeter-wave and lightwave electric fields in electro-optic modulation. Analysis and experimentally demonstration of the proposed device are discussed and reported for 40GHz millimeter-wave bands. Optical millimeter-wave radar beam-forming in 2-D is also discussed.

A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low-power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, Cu-Al alloy or CoWP cap-metal is quite effective for boosting reliability.

This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.

We report 0.15-µm T-shaped gate MODFETs using BCB (Benzocyclobutene) as low-k spacer dielectric material. The RF performance of pseudomorphic MODFET was improved by reducing the gate fringing capacitance using low-k material. The BCB film was deposited by plasma CVD technique at 100C and was patterned by lift-off technique. The dielectric constant of BCB film deposited by plasma CVD was confirmed 2.7, which is equal to that of spin-coated BCB, and is 35% lower than that of conventional SiO2. The leakage current was 4.710-5 A/cm2 at 3.6 MV/cm and was low enough for spacer material. 0.15-µm T-shaped gate MODFETs were fabricated by using BCB spacer and phase-shift lithography technique. More than 20 GHz increase of fmax was obtained in comparison with conventional SiO2 spacer by reducing the gate fringing capacitance.

The performance of copper interconnects formed by the low-kinetic-energy ion bombardment process has been investigated. The copper films formed on SiO2 by this technology under a sufficient amount of ion energy deposition exhibit perfect orientation conversion from Cu (111) to Cu (100) upon post-metallization thermal annealing. We have discovered such crystal orientation conversion is always accompanied by a giant-grain growth as large as 100 µm. The copper film resistivity decreases due to the decrease in the grain boundary scattering, when the giant-grain growth occurs in the film. The resistivity of giant-grain copper film at a room temperature is 1.76 µΩcm which is almost equal to the bulk resistivity of copper. Furthermore, a new-accelerated electromigration life-test method has been developed to evaluate copper interconnects having large electromigration resistance within a very short period of test time. The essence of the new method is the acceleration by a large-current-stress of more than 107 A/cm2 and to utilize the self heating of test interconnect for giving temperature stress. In order to avoid uncontrollable thermal runaway and resultant interconnect melting, we adopted a very efficient cooling system that immediately removes Joule heat and keeps the interconnect temperature constant. As a result, copper interconnects formed by the low-kinetic-energy ion bombardment process exhibit three orders of magnitude longer lifetime at 300 K than Al alloy interconnects.