This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.

This paper proposes a new efficient method of characterizing a memory compiler in order to reduce the computation time and remove human error. The new features that make our method greatly efficient are the following three points: (1) high-speed circuit simulation of the whole memory module using a hierarchical LPE (Layout Parasitic Extractor) and a hierarchical circuit simulator, (2) automatic generation of circuit simulation input data from corresponding parameterized description termed the template file, and (3) carefully selected environmental conditions of circuit level simulator and minimizing the number of runs of it. We demonstrate the effectiveness of the proposed method by application to the single-port SRAM generators using 90 nm CMOS technology.