A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
Summary :
This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3463-3470
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3463
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Interconnect
Authors
Toshiki KANAMOTO
Tetsuya WATANABE
Mitsutoshi SHIROTA
Masayuki TERAI
Tatsuya KUNIKIYO
Kiyoshi ISHIKAWA
Yoshihide AJIOKA
Yasutaka HORIBA
Keyword
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Toshiki KANAMOTO, Tetsuya WATANABE, Mitsutoshi SHIROTA, Masayuki TERAI, Tatsuya KUNIKIYO, Kiyoshi ISHIKAWA, Yoshihide AJIOKA, Yasutaka HORIBA, "A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3463-3470, December 2005, doi: 10.1093/ietfec/e88-a.12.3463.
Abstract: This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3463/_p
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@ARTICLE{e88-a_12_3463,
author={Toshiki KANAMOTO, Tetsuya WATANABE, Mitsutoshi SHIROTA, Masayuki TERAI, Tatsuya KUNIKIYO, Kiyoshi ISHIKAWA, Yoshihide AJIOKA, Yasutaka HORIBA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures},
year={2005},
volume={E88-A},
number={12},
pages={3463-3470},
abstract={This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3463},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3463
EP - 3470
AU - Toshiki KANAMOTO
AU - Tetsuya WATANABE
AU - Mitsutoshi SHIROTA
AU - Masayuki TERAI
AU - Tatsuya KUNIKIYO
AU - Kiyoshi ISHIKAWA
AU - Yoshihide AJIOKA
AU - Yasutaka HORIBA
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3463
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.
ER -
English
