In a field of biomedical engineering, not only low-pass filters for high frequency elimination but also notch filters for suppressing powerline interference are necessary to process low-frequency biosignals. For integration of low-frequency filters, chip implementation of large capacitances is major difficulty. As methods to enhance capacitances with small chip area, use of capacitance multipliers is effective. This letter describes design consideration of integrated low-frequency low-pass notch filter employing capacitance multipliers. Two main points are presented. Firstly, a new floating capacitance multiplier is proposed. Secondly, a technique to reduce the number of capacitance multipliers is proposed. By this technique, power consumption is reduced. The proposed techniques are applied a 3rd order low-pass notch filter. Simulation results show the effectiveness of the proposed techniques.

Aiming at the problem of the deterioration of the contact performance caused by the wear debris generated during the fretting wear of the electrical connector, low-frequency fretting wear experiments were carried out on the contacts of electrical connectors, the accumulation and distribution of the wear debris were detected by the electrical capacitance tomography technology; the influence of fretting cycles, vibration direction, vibration frequency and vibration amplitude on the accumulation and distribution of wear debris were analyzed; the correlation between characteristic value of wear debris and contact resistance value was studied, and a performance degradation model based on the accumulation and distribution of wear debris was built. The results show that fretting wear and performance degradation are the most serious in axial vibration; the characteristic value of wear debris and contact resistance are positively correlated with the fretting cycles, vibration frequency and vibration amplitude; there is a strong correlation between the sum of characteristic value of wear debris and the contact resistance value; the prediction error of ABC-SVR model of fretting wear performance degradation of electrical connectors constructed by the characteristic value of wear debris is less than 6%. Therefore, the characteristic value of wear debris in contact subareas can quantitatively describe the degree of fretting wear and the process of performance degradation.

In this paper, the author performed an electromagnetic field simulation of a typical bonding wire structure that connects a chip and a package, and evaluated the signal transmission characteristics (S-parameters). In addition, the inductance per unit length was extracted by comparing with the equivalent circuit of the distributed constant line. It turns out that the distributed constant line model is not sufficient because there are frequencies where chip-package resonance occurs. Below the resonance frequency, the conventional low-frequency approximation model was effective, and it was found that the inductance was about 1nH/mm.

Capacitive coupling of line coded and DC-balanced digital signals is often used to eliminate steady bias current flow between the systems or components in various communication systems. A multi-layer ceramic chip capacitor is promising for the capacitor of very broadband signal coupling because of its high frequency characteristics expected from the downsizing of the chip recent years. The lower limit of the coupling bandwidth is determined by the capacitance while the higher limit is affected by the parasitic inductance associated with the chip structure. In this paper, we investigate the coupling characteristics up to millimeter wave frequencies by the measurement and simulations. A phenomenon has been found in which the change in the current distribution in the chip structure occur at high frequencies and the coupling characteristics are improved compared to the prediction based on the conventional equivalent circuit model. A new equivalent circuit model of chip capacitor that can express the effect of the improvement has been proposed.

This paper describes a method of measuring the unsymmetric voltage of conducted noise using a floating measurement system. Here, floating means that there is no physical connection to the reference ground. The method works by correcting the measured voltage to the desired unsymmetric voltage using the capacitance between the measurement instrument and the reference ground plane acting as the return path of the conducted electromagnetic noise. The existing capacitance measurement instrument needs a probe in contact with the ground, so it is difficult to use for on-site measurement of stray capacitance to ground at troubleshooting sites where the ground plane is not exposed or no ground connection point is available. The authors have developed a method of measuring stray capacitance to ground that does not require physical connection of the probe to the ground plane. The developed method can be used to estimate the capacitance between the measurement instrument and ground plane even if the distance and relative permittivity of the space are unknown. And a method is proposed for correcting the voltage measured with the floating measurement system to obtain the unsymmetric voltage of the noise by using the measured capacitance to ground. In the experiment, the unsymmetric voltage of a sinusoidal wave transmitting on a co-axial cable was measured with a floating oscilloscope in a shield room and the measured voltage was corrected to within 2dB of expected voltage by using the capacitance measured with the developed method. In addition, the voltage of a rectangular wave measured with the floating oscilloscope, which displays sag caused by the stray capacitance to ground, was corrected to a rectangular wave without sag. This means that the phase of the unsymmetric voltage can also be corrected by the measured stray capacitance. From these results, the effectiveness of the proposed methods is shown.

In IoT (Internet-of-Things) era, the number and variety of hardware devices becomes continuously increasing. Several IoT devices are utilized at infrastructure equipments. How to maintain such IoT devices is a serious concern. Capacitance measurement is one of the powerful ways to detect anomalous states in the structure of the hardware devices. Particularly, measuring capacitance while the hardware device is running is a major challenge but no such researches proposed so far. This paper proposes a capacitance measuring device which measures device capacitance in operation. We firstly combine the AC (alternating current) voltage signal with the DC (direct current) supply voltage signal and generates the fluctuating signal. We supply the fluctuating signal to the target device instead of supplying the DC supply voltage. By effectively filtering the observed current in the target device, the filtered current can be proportional to the capacitance value and thus we can measure the target device capacitance even when it is running. We have implemented the proposed capacitance measuring device on the printed wiring board with the size of 95mm × 70mm and evaluated power consumption and accuracy of the capacitance measurement. The experimental results demonstrate that power consumption of the proposed capacitance measuring device is reduced by 65% in low-power mode from measuring mode and proposed device successfully measured capacitance in 0.002μF resolution.

An electrical capacitance tomography (ECT) method was used to detect fretting wear behavior of electrical connectors. The specimens used in this study were contacts of type-M round two-pin electrical connectors. The experiments consisted of running a series of vibration tests at each frequency combined with one g levels. During each test run, the measured capacitance per pair of electrodes was monitored as a performance characteristic, which is induced by the wear debris generated by the fretting wear of electrical connectors. The fretted surface is examined using scanning electron microscopy (SEM) and energy dispersive spectrometer (EDS) analysis to assess the surface profile, extent of fretting damage and elemental distribution across the contact zone and then compared to the capacitance values. The results exhibit that with the increase of the fretting cycles or the vibration frequency, the characteristic value of the wear debris between the contacts of electrical connector gradually increases and the wear is more serious. Measured capacitance values are consistent with SEM and EDS analysis.

An LLC converter has high efficiency and low noise and has thus recently attracted attention in the field of power supplies for use in information and communication systems. A planar transformer is thought to be particularly effective in a high-frequency switching power supply because an ideal primary-secondary interleave structure can be formed by the multilayer structure, and the alternating-current (AC) resistance can be reduced. Based on these facts, we investigated the use of planar transformers in LLC converters. However, high-frequency oscillation, which is not observed in a normal winding transformer, appears in the secondary side current, and the power supply loss is also higher. Our investigation found that the current oscillation and an increase in loss were caused by a primary-secondary capacitance of the transformer. This paper presents countermeasures used to reduce the capacitance between the primary and secondary windings, and a new layer structure for the transformer that reduces the capacitance. The loss is calculated through a simulation and experimentally, and good agreement is obtained. The proposed transformer offers the high efficiency of 98.1% in a 200 W, 12 V output power supply.

The major task in compact modeling for high power devices is to predict the switching waveform accurately because it determines the energy loss of circuits. Device capacitance mainly determines the switching characteristics, which makes accurate capacitance modeling inevitable. This paper presents a newly developed compact model HiSIM-GaN [Hiroshima University STARC IGFET Model for Gallium-Nitride-based High Electron Mobility Transistors (GaN-HEMTs)], where the focus is given on the accurate modeling of the field-plate (FP), which is introduced to delocalize the electric-field peak that occurs at the electrode edge. We demonstrate that the proposed model reproduces capacitance measurements of a GaN-HEMT accurately without fitting parameters. Furthermore, the influence of the field plate on the studied circuit performance is analyzed.

Two-port SRAMs are frequently installed in gate-array VLSIs to implement smart functions. This paper presents a new high-density 10T CMOS base cell for gate-array-based two-port SRAM applications. Using the single base cell alone, we can implement a two-port memory cell whose bitline contacts are shared with the memory cell adjacent to one of two dedicated sides, resulting in greatly reduced parasitic capacitance in bitlines. To throw light on the total performance derived from the base cell, a plain two-port SRAM macro was designed and fabricated with a 0.35-µm low cost, logic process. Each of two 10-bit power-saved address decoders was formed with 36% fewer base cells by employing complex gates and a subdecoder. The new sense amplifier with a complementary sensing scheme had a fine sensitivity of 35 mVpp, and so we successfully reduced the required read bitline signal from 250 to 70 mVpp. With the macro with 1024 memory cells per bitline, the address access time under typical conditions of a 2.5-V power supply and 25°C was 4.0 ns (equal to that obtained with full-custom style design) and the power consumption at 200-MHz simultaneous operations of two ports was 6.7 mW for an I/O-data width of 1 bit.

A negative capacitor is fabricated using poly(vinylidene fluoride-trifluoroethylene) copolymer and connected in series to an a-IZO TFT. It is experimentally demonstrated that the negative capacitance of the negative capacitor can create steep switching in the a-IZO TFT (e.g., a subthreshold slope change from 342mV/decade to 102mV/decade at room-temperature).

A novel directional coupler loaded with feedback capacitances on the coupled lines is presented. Its effect of enhancing the coupling is qualitatively shown by deriving an equation for the coupling. Besides, a method to compensate for the phase difference between the even and odd modes of the coupler is presented. To demonstrate, a novel tandem 3-dB coupler consisting of the proposed coupled lines is designed and described. In addition, a waveguide (rectangular coaxial line) 8×8 HYB matrix using planar double-layer structure that is composed of the proposed tandem 3-dB couplers and branch-line couplers, which is operated in S-band, is designed and fabricated showing excellent performance.

This paper presents a 20GHz Class-C VCO using a noise sensitivity mitigation technique. A radio frequency Class-C VCO suffers from the AM-PM conversion, caused by the non-linear capacitance of cross coupled pair. In this paper, the phase noise degradation mechanism is discussed, and a desensitization technique of AM-PM noise is proposed. In the proposed technique, AM-PM sensitivity is canceled by tuning the tail impedance, which consists of 4-bit resistor switches. A 65-nm CMOS prototype of the proposed VCO demonstrates the oscillation frequency from 19.27 to 22.4GHz, and the phase noise of -105.7dBc/Hz at 1-MHz offset with the power dissipation of 6.84mW, which is equivalent to a Figure-of-Merit of -183.73dBc/Hz.

We have developed a capacitance sensor of frequency modulation for integrated touchpanels using amorphous In-Sn-Zn-O (α-ITZO) thin-film transistors (TFTs). This capacitance sensor consists of a ring oscillator, whose one stage is replaced by a reset transistor, sensing transistor, and sensing electrode. The sensing electrode is prepared as one terminal to form a sensing capacitor when the other terminal is added by a finger. The ring oscillator consists of pseudo CMOS inverters. We confirm that the oscillation frequency changes when the other terminal is added. This result suggests that this capacitance sensor can be applied to integrated touchpanels on flatpanel displays.

We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal--oxide--metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50,dB (8 bits) is achievable at an input signal frequency of 78,kHz and a sampling rate of 20,MHz, where the respective area and power are 6468,mm$^{mathrm{2}}$ and 509 $mu$W. The measured maximum integral nonlinearity (INL) of the proposed ADC is $-$1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.

Fast simulation techniques of large scale RLC networks with nonlinear devices are presented. Generally, when scale of nonlinear part in a circuit is much less than the linear part, matrix or circuit partitioning approach is known to be efficient. In this paper, these partitioning techniques are used for the conventional transient analysis using an implicit numerical integration and the circuit-based finite-difference time-domain (FDTD) method, whose efficiency and accuracy are evaluated developing a prototype simulator. It is confirmed that the matrix and circuit partitioning approaches do not degrade accuracy of the transient simulations that is compatible to SPICE, and that the circuit partitioning approach is superior to the matrix one in efficiency. Moreover, it is demonstrated that the circuit-based FDTD method can be efficiently combined with the matrix or circuit partitioning approach, compared with the transient analysis using an implicit numerical integration.

This letter proposes a wideband compact DC block design technique. This DC block has a wide pass-band and wide stop-band and transforms termination impedances. It comprises a pair of coupled lines on a defected ground structure (DGS) with capacitor loading. A periodic DGS pattern increases coupling, and, consequently, a wideband DC block design is allowed with a microstrip process on a high dielectric low height substrate. A DC block with equal termination impedances of 50,$Omega$ and another that transforms 50 into 30,$Omega$ are fabricated. The measured fractional bandwidths are 48% and 47%. The size of the DC block is 16.8$ imes$ 15,mm$^2(0.057lambda_0 imes 0.051lambda_0)$.

In this paper, the measurement of capacitance variation, of an on-chip power distribution network (PDN) due to the change of internal states of a CMOS logic circuit, is studied. A state-dependent PDN-capacitance model that explains measurement results will be also proposed. The model is composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate. Reflecting the changes of electrode potentials, the capacitance elements become state-dependent. The capacitive elements are then all connected in parallel between power supply and ground to form the proposed model. By using the proposed model, state-dependence of PDN-capacitances for different logic circuits are studied in detail. The change of PDN-capacitance exceeds 12% of its total capacitance in some cases, which corresponds to 6% shift of anti-resonance frequency. Consideration of the state-dependence is important for modeling the PDN-capacitance.

This paper describes a very accurate method of estimating the return-path-capacitance and validates the estimation based on low-error measurements for electric-field intrabody communication. The return-path capacitance, Cg, of a mobile transceiver is estimated in two ways. One uses the attenuation factor in transmission and capacitance, Cb, between a human body and the earth ground. The other uses the attenuation factor in reception. To avoid the influence of the lead wire in the estimation of Cb, Cb is estimated from the attenuation factor measured with an amplifier with a low input capacitance. The attenuation factor in reception is derived by using the applied-voltage dependence of the reception rate. This way avoids the influence of any additional instruments on the return-path capacitance and allows that capacitance to be estimated under the same condition as actual intrabody communication. The estimates obtained by the two methods agree well with each other, which means that the estimation of Cb is valid. The results demonstrate the usefulness of the methods.

Open faults are difficult to test since the voltage at the floating line is unpredictable and depends on the voltage at the adjacent lines. The effect of open faults can be easily excited if a test pattern provides the opposite logic value to most of the adjacent lines. In this paper, we present a procedure to generate as high a quality test as possible. We define the test quality for evaluating the effect of adjacent lines by assigning an opposite logic value to the faulty line. In our proposed test generation method, we utilize the SAT-based ATPG method. We generate test patterns that propagate the faulty effect to primary outputs and assign logic values to adjacent lines opposite that of the faulty line. In order to estimate test quality for open faults, we define the excitation effectiveness Eeff. To reduce the test volume, we utilize the open fault simulation. We calculate the excitation effectiveness by open fault simulation in order to eliminate unnecessary test patterns. The experimental results for the benchmark circuits prove the effectiveness of our procedure.