An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter
Summary :
We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal–oxide–metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm2 and 509 μW. The measured maximum integral nonlinearity (INL) of the proposed ADC is -1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E98-C No.6 pp.489-495
- Publication Date
- 2015/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E98.C.489
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Keisuke OKUNO
Kobe University
Toshihiro KONISHI
Kobe University
Shintaro IZUMI
Kobe University
Masahiko YOSHIMOTO
Kobe University
Hiroshi KAWAGUCHI
Kobe University
Keyword
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Keisuke OKUNO, Toshihiro KONISHI, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, "An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter" in IEICE TRANSACTIONS on Electronics,
vol. E98-C, no. 6, pp. 489-495, June 2015, doi: 10.1587/transele.E98.C.489.
Abstract: We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal–oxide–metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm2 and 509 μW. The measured maximum integral nonlinearity (INL) of the proposed ADC is -1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.489/_p
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@ARTICLE{e98-c_6_489,
author={Keisuke OKUNO, Toshihiro KONISHI, Shintaro IZUMI, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter},
year={2015},
volume={E98-C},
number={6},
pages={489-495},
abstract={We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal–oxide–metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm2 and 509 μW. The measured maximum integral nonlinearity (INL) of the proposed ADC is -1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.},
keywords={},
doi={10.1587/transele.E98.C.489},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 489
EP - 495
AU - Keisuke OKUNO
AU - Toshihiro KONISHI
AU - Shintaro IZUMI
AU - Masahiko YOSHIMOTO
AU - Hiroshi KAWAGUCHI
PY - 2015
DO - 10.1587/transele.E98.C.489
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2015
AB - We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal–oxide–metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm2 and 509 μW. The measured maximum integral nonlinearity (INL) of the proposed ADC is -1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.
ER -
English
