A negative capacitor is fabricated using poly(vinylidene fluoride-trifluoroethylene) copolymer and connected in series to an a-IZO TFT. It is experimentally demonstrated that the negative capacitance of the negative capacitor can create steep switching in the a-IZO TFT (e.g., a subthreshold slope change from 342mV/decade to 102mV/decade at room-temperature).

To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.