Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method
Summary :
To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.5 pp.541-543
- Publication Date
- 2016/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.541
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
Sangheon OH
University of Seoul
Changhwan SHIN
University of Seoul
Keyword
Latest Issue
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Sangheon OH, Changhwan SHIN, "Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 5, pp. 541-543, May 2016, doi: 10.1587/transele.E99.C.541.
Abstract: To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.541/_p
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@ARTICLE{e99-c_5_541,
author={Sangheon OH, Changhwan SHIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method},
year={2016},
volume={E99-C},
number={5},
pages={541-543},
abstract={To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.},
keywords={},
doi={10.1587/transele.E99.C.541},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method
T2 - IEICE TRANSACTIONS on Electronics
SP - 541
EP - 543
AU - Sangheon OH
AU - Changhwan SHIN
PY - 2016
DO - 10.1587/transele.E99.C.541
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2016
AB - To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.
ER -
English
