Timing fault detection techniques address the problems caused by increased variations on a chip, especially with dynamic voltage and frequency scaling (DVFS). The Razor flip-flop (FF) is a timing fault detection technique that employs double sampling by the main and shadow FFs. In order for the Razor FF to correctly detect a timing fault, not the main FF but the shadow FF must sample the correct value. The application of Razor FFs to static logic relaxes the timing constraints; however, the naive application of Razor FFs to dynamic precharged logic such as SRAM read circuits is not effective. This is because the SRAM precharge cannot start before the shadow FF samples the value; otherwise, the transition of the bitline of the SRAM stops and the value sampled by the shadow FF will be incorrect. Therefore, the detect period cannot overlap the precharge period. This paper proposes a novel application of Razor FFs to SRAM read circuits. Our proposal employs a conditional precharge according to the value of a bitline sampled by the main FF. This enables the detect period to overlap the precharge period, thereby relaxing the timing constraints. The additional circuit required by this method is simple and only needed around the sense amplifier, and there is no need for a clock delayed from the system clock. Consequently, the area overhead of the proposed circuit is negligible. This paper presents SPICE simulations of the proposed circuit. Our proposal reduces the minimum cycle time by 51.5% at a supply voltage of 1.1 V and the minimum voltage by 31.8% at cycle time of 412.5 ps.

To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.

We propose guidelines for LSI-chip design, taking the within-die variations into consideration, and for process quality improvement to suppress the variations. The auto-correlation length, λ, of device variation is shown to be a useful measure to treat the systematic variations in a chip. We may neglect the systematic variation in chips within the range of λ, while σ2 of the systematic variation must be added to σ2 of the random variation outside the λ. The random variations, on the other hand, exhibit complete randomness even in the closest pair transistors. The mismatch variations in transistor pairs were enhanced by 1.41(=) compared with the random variations in single transistors. This requires careful choice of gate size in designing a transistor pair with a minimum size, such as transfer gates in an SRAM cell. Poly-Si gate formation is estimated to be the most important process to ensure the spatial uniformity in transistor current and to enhance circuit performance. Large relative variations are observed for the contact to p+ diffusion, via1 (M1-M2), and via2 (M2-M3) among parameter variations in passive elements. The standard deviations for random variations in via1 and via2 are noticeably widespread, indicating the importance of the via resistance control in BEOL. The spatial frequency power spectrum for within-die random variations is confirmed experimentally, as uniform ('white') with respect to the spatial frequency. To treat the large 'white random noise,' the least-square method with a 4th-order polynomial exhibits a best efficiency as a fitting function for decomposing the raw variation data into systematic part and random part.