IEICE TRANSACTIONS on Fundamentals
A Fast Characterizing Method for Large Embedded Memory Modules on SoC
Summary :
This paper proposes a new efficient method of characterizing a memory compiler in order to reduce the computation time and remove human error. The new features that make our method greatly efficient are the following three points: (1) high-speed circuit simulation of the whole memory module using a hierarchical LPE (Layout Parasitic Extractor) and a hierarchical circuit simulator, (2) automatic generation of circuit simulation input data from corresponding parameterized description termed the template file, and (3) carefully selected environmental conditions of circuit level simulator and minimizing the number of runs of it. We demonstrate the effectiveness of the proposed method by application to the single-port SRAM generators using 90 nm CMOS technology.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.4 pp.815-822
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.4.815
- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Category
Authors
Keyword
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Masahiko OMURA, Toshiki KANAMOTO, Michiko TSUKAMOTO, Mitsutoshi SHIROTA, Takashi NAKAJIMA, Masayuki TERAI, "A Fast Characterizing Method for Large Embedded Memory Modules on SoC" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 4, pp. 815-822, April 2007, doi: 10.1093/ietfec/e90-a.4.815.
Abstract: This paper proposes a new efficient method of characterizing a memory compiler in order to reduce the computation time and remove human error. The new features that make our method greatly efficient are the following three points: (1) high-speed circuit simulation of the whole memory module using a hierarchical LPE (Layout Parasitic Extractor) and a hierarchical circuit simulator, (2) automatic generation of circuit simulation input data from corresponding parameterized description termed the template file, and (3) carefully selected environmental conditions of circuit level simulator and minimizing the number of runs of it. We demonstrate the effectiveness of the proposed method by application to the single-port SRAM generators using 90 nm CMOS technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.4.815/_p
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@ARTICLE{e90-a_4_815,
author={Masahiko OMURA, Toshiki KANAMOTO, Michiko TSUKAMOTO, Mitsutoshi SHIROTA, Takashi NAKAJIMA, Masayuki TERAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Characterizing Method for Large Embedded Memory Modules on SoC},
year={2007},
volume={E90-A},
number={4},
pages={815-822},
abstract={This paper proposes a new efficient method of characterizing a memory compiler in order to reduce the computation time and remove human error. The new features that make our method greatly efficient are the following three points: (1) high-speed circuit simulation of the whole memory module using a hierarchical LPE (Layout Parasitic Extractor) and a hierarchical circuit simulator, (2) automatic generation of circuit simulation input data from corresponding parameterized description termed the template file, and (3) carefully selected environmental conditions of circuit level simulator and minimizing the number of runs of it. We demonstrate the effectiveness of the proposed method by application to the single-port SRAM generators using 90 nm CMOS technology.},
keywords={},
doi={10.1093/ietfec/e90-a.4.815},
ISSN={1745-1337},
month={April},}
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TY - JOUR
TI - A Fast Characterizing Method for Large Embedded Memory Modules on SoC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 815
EP - 822
AU - Masahiko OMURA
AU - Toshiki KANAMOTO
AU - Michiko TSUKAMOTO
AU - Mitsutoshi SHIROTA
AU - Takashi NAKAJIMA
AU - Masayuki TERAI
PY - 2007
DO - 10.1093/ietfec/e90-a.4.815
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2007
AB - This paper proposes a new efficient method of characterizing a memory compiler in order to reduce the computation time and remove human error. The new features that make our method greatly efficient are the following three points: (1) high-speed circuit simulation of the whole memory module using a hierarchical LPE (Layout Parasitic Extractor) and a hierarchical circuit simulator, (2) automatic generation of circuit simulation input data from corresponding parameterized description termed the template file, and (3) carefully selected environmental conditions of circuit level simulator and minimizing the number of runs of it. We demonstrate the effectiveness of the proposed method by application to the single-port SRAM generators using 90 nm CMOS technology.
ER -
English
