IEICE TRANSACTIONS on Electronics
Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link
Summary :
A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18 µm CMOS process. With a pair of 700
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.2 pp.164-171
- Publication Date
- 2010/02/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.164
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Yuxiang YUAN, Yoichi YOSHIDA, Tadahiro KURODA, "Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 2, pp. 164-171, February 2010, doi: 10.1587/transele.E93.C.164.
Abstract: A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18 µm CMOS process. With a pair of 700
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.164/_p
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@ARTICLE{e93-c_2_164,
author={Yuxiang YUAN, Yoichi YOSHIDA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link},
year={2010},
volume={E93-C},
number={2},
pages={164-171},
abstract={A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18 µm CMOS process. With a pair of 700
keywords={},
doi={10.1587/transele.E93.C.164},
ISSN={1745-1353},
month={February},}
Copy
TY - JOUR
TI - Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link
T2 - IEICE TRANSACTIONS on Electronics
SP - 164
EP - 171
AU - Yuxiang YUAN
AU - Yoichi YOSHIDA
AU - Tadahiro KURODA
PY - 2010
DO - 10.1587/transele.E93.C.164
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2010
AB - A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18 µm CMOS process. With a pair of 700
ER -
English
