This work presents an FSK inductive-coupling transceiver using a load-modulated transmitter and LC-oscillator-based receiver for energy-budget-unbalanced applications. By introducing the time-domain load modulated transmitter for FSK instead of the conventional current-driven scheme, energy reduction of the transmitter side is possible. For verifying the proposed scheme, a test chip was fabricated in 65nm CMOS, and two chips were stacked for verifying the inter-chip communication. The measurement results show 0.64fJ/bit transmitter power consumption while its input voltage is 60mV, and the communication distance is 150μm. The footprint of the transmitter is 0.0016mm2.

TSV-interconnected 3D chips face problems such as high cost, low yield and large power dissipation. We propose a wireless 3D on-chip-network architecture for application-specific SoC design, using inductive-coupling interconnect instead of TSV for inter-layer communication. Primary design challenge of inductive-coupling 3D SoC is allocating wireless links in the 3D on-chip network effectively. We develop a design flow fully exploiting the design space brought by wireless links while providing flexible tradeoff for user's choice. Experimental results show that our design brings great improvement over uniform design and Sunfloor algorithm on latency (5% to 20%) and power consumption (10% to 45%).

We propose low-power techniques for wireless three-dimensional Network-on-Chips (wireless 3-D NoCs), in which the connections among routers on the same chip are wired while the routers on different chips are connected wirelessly using inductive-coupling. The proposed low-power techniques stop the clock and power supplies to the transmitter of the wireless vertical links only when their utilizations are higher than the threshold. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold in order to reduce the power consumption of wireless 3-D NoCs. This paper uses an on-demand method, in which the dormant data transmitter or the whole vertical link will be activated as long as a flit comes. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 23.4%-29.3%, while the performance overhead is less than 2.4%.

A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18 µm CMOS process. With a pair of 700700 µm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36 mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size .