This paper formulates a class-E synchronous RF rectifier from a new viewpoint. The key point is to introduce a matrix and convolute the DC terms into RF matrices. The explicit expression of input impedance is demonstrated in plane geometry. We find out their input impedance exhibits a geodesic arc in hyperbolic geometry under ZVS operation, where the theoretical RF-DC conversion efficiency results in 100%. We verify the developed theory both numerically (circuit simulation) and experimentally (6.78MHz, 100W). We confirm that the input impedance becomes a geodesic arc for a wide range of DC load resistance. The presented theory is quite elegant since it is based on a matrix-based formulation and plane-geometrical expression.

This study proposes a new structure of a single-shunt rectifier circuit that can reduce circuit loss and improve efficiency over the conventional structure. The proposed structure can provide impedance matching to the measurement system (or receiving antenna) without the use of conventional matching circuits, such as stubs and tapers. The proposed structure can simultaneously perform full-wave rectification and impedance matching by placing a feeding point on the output filter's λ/4 transmission line. We use circuit simulation to compare the RF-DC conversion efficiency and circuit loss of the conventional and proposed structures. The simulation results show that the proposed structure has lower circuit loss and higher RF-DC conversion efficiency than the conventional structure. We fabricate the proposed rectifier circuit using a GaAs Schottky barrier diode. The simulation and measurement results show that the single-shunt rectifier circuit's proposed structure is capable of rectification and impedance matching. The fabricated rectifier circuit's RF-DC conversion efficiency reaches a maximum of 91.0%. This RF-DC conversion efficiency is a world record for 920-MHz band rectifier circuits.

In the conventional single-phase PWM rectifier, the sinusoidal fluctuating current and voltage on the grid side will generate power ripple with a doubled grid frequency which leads to a secondary ripple in the DC output voltage, and the switching frequency of the conventional model predictive control strategy is not fixed. In order to solve the above two problems, a control strategy for suppressing the secondary ripple based on the three-vector fixed-frequency model predictive current control is proposed. Taking the capacitive energy storage type single-phase PWM rectifier as the research object, the principle of its active filtering is analyzed and a model predictive control strategy is proposed. Simulation and experimental results show that the proposed strategy can significantly reduce the secondary ripple of the DC output voltage, reduce the harmonic content of the input current, and achieve a constant switching frequency.

In this paper, a high-efficiency high-power rectenna with a bridge diode and the diode on antenna (DoA) topology is discussed. First, the topologies of rectifiers and rectennas are discussed to indicate the direction for obtaining highly efficient rectification. Rectifiers with well-matched diode pairs, as double voltage and bridge rectifiers, can reactively terminate even order harmonics, and is suitable for highly efficient operation. A rectenna with the DoA topology is suitable for a direct connection between the highly functional antenna and the rectifier diodes to remove lossy circuit portions. Next, the formulas for the rectification efficiency of the bridge rectifier are demonstrated with the behavioral model. The indicated formulas clarify the fundamental limitation on the rectification efficiency, which is the design goal in case of the DoA topology. Finally, we demonstrate a 5.8 GHz band 1 W rectenna with the bridge diode and the DoA topology. The bridge rectifier that is directly connected to the inductive high-impedance antenna achieved a rectification efficiency of 92.8% at an input power of 1 W. This is close to the fundamental limitation due to the diode performance.

Research on wireless power transmission technology is being actively conducted, and studies on spatial transmission methods such as SSPS are currently underway for applications such as power transfer to the upper part of steel towers and power transfer to flying objects such as drones. To enable such applications, it is necessary to examine the configuration of the power-transfer and power-receiving antennas and to improve the RF-DC conversion efficiency (hereinafter referred to as conversion efficiency) of the rectifier circuit on the power-receiving antenna. To improve the conversion efficiency, various methods that utilize full-wave rectification rather than half-wave rectification have been proposed. However, these come with problems such as a complicated circuit structure, the need for additional capacitors, the selection of components at high frequencies, and a reduction in mounting yield. In this paper, we propose a method to improve the conversion efficiency by loading a high-impedance microstrip line as a feedback line in part of the rectifier circuit. We analyzed a class-F rectifier circuit using circuit analysis software and found that the conversion efficiency of the conventional configuration was 54.2%, but the proposed configuration was 69.3%. We also analyzed a measuring circuit made with a discrete configuration in the 5.8-GHz band and found that the conversion efficiency was 74.7% at 24dBm input.

This study proposes a design method for a rectifier circuit that can be rapidly charged by focusing on the design-load value of the circuit and the load fluctuation of a storage capacitor. The design-load value is suitable for rapidly charging the capacitor. It can be obtained at the lowest reflection condition and estimated according to the circuit design. This is a conventional method for designing the rectifier circuit using the optimum load. First, we designed rectifier circuits for the following three cases. The first circuit design uses a load set to 10 kΩ. The second design uses a load of 30 kΩ that is larger than the optimum load. The third design utilizes a load of 3 kΩ. Then, we measure the charging time to design the capacitor on each circuit. Consequently, the results show that the charge time could be shortened by employing the design-load value lower than that used in the conventional design. Finally, we discuss herein whether this design method can be applied regardless of the rectifier circuit topology.

This work reports a new technique to suppress the undesirable multiple-triggering effect in the typical diode triggered silicon controlled rectifier (DTSCR), which is frequently used as an ESD protection element in the advanced CMOS technologies. The technique is featured by inserting additional N-Well areas under the N+ region of intrinsic SCR, which helps to improve the substrate resistance. As a consequence, the delay of intrinsic SCR is reduced as the required triggering current is largely decreased and multiple-triggering related higher trigger voltage is removed. The novel DTSCR structures can alter the stacked diodes to achieve the precise trigger voltage to meet different ESD protection requirements. All explored DTSCR structures are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and Very-Fast-Transmission-line-pulsing (VF-TLP) test systems are adopted to confirm the validity of this technique and the test results accord well with our analysis.

In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (Vh) and high triggering voltage (Vt1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate Vt1 of 6.3 V, high Vh of 4.2 V, high normalized second breakdown current (It2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

This paper looks into the underlying RF energy harvesting issues at low input ambient power levels below 0 dBm where efficiency degradation is severe. The proposed design aims to improve the rectenna sensitivity, efficiency, and output DC power. In the same manner, we are using a straightforward and compact size rectenna design. The receiving antenna is a coplanar waveguide (CPW) slot monopole antenna with harmonic suppression property and a peak measured gain of 3 dBi. Also, an improved antenna radiation characteristics, e.g radiation pattern and gain covering the desired operating band (ISM 2.45 GHz), is observed. The rectifier is a voltage doubler circuit based on microstrip (MS) structure. Two architectures of rectenna were carefully designed, fabricated and tested. The first layout; antenna, and rectifier were fabricated separately and then connected using a connector. The peak efficiency (40% at -5 dBm) achieved is lower than expected. To improve the efficiency, a high compactness and simple integration between antenna and rectifier are achieved by using a smooth CPW-MS transition. This design shows improved conversion efficiency measurement results which typically agree with the simulation results. The measured peak conversion efficiency is 72% at RF power level of -7 dBm and a load resistance of 2 kΩ.

This paper presents an approach to nonlinear impedance measurement exploiting an oscilloscope and Möbius transformation. Proposed system consists of a linear 4-port network and an oscilloscope. One of the port is excited by a high power source. The power is delivered to the second port, which is loaded with a DUT. Another set of two ports are used to observe a voltage set. This voltage set gives the impedance of the DUT through Möbius transformation. We formulated measurability M of the system, and derived the condition that M becomes constant for any DUT. To meet the condition, we propose a linear 4-port network consisting of a quarter-wavelength transmission line and resistors. We confirm the validity and utility of the proposed system by measuring the impedance of incandescent bulbs and an RF diode rectifier.

Novel design approaches for microwave active circuits using composite right-/left-handed (CRLH) transmission line (TL) stubs are presented. We show that, by modifying the dispersion diagram of the CRLH TL stub, the frequency band or the harmonic tuning capability can be enhanced in such a way that it would have been difficult or impractical if done using conventional micro-strip line stubs. The frequency response of the CRLH TL stub can be controlled almost arbitrarily while at the same time reducing the stub length significantly, because the dispersion curve in the left-handed region and in the right-handed region is controlled independently. As a proof of concept, a triple-band rectifier, single-band and dual-band harmonic tuning circuits for class-F amplifiers are demonstrated.

To improve the quality of waveforms and achieve a high input power factor (IPF) for matrix rectifier, a novel quasi sliding mode control (SMC) with adaptive compensation is proposed in this letter. Applying quasi-SMC can effective obviate the disturbances of time delay and spatial lag, and SMC based on continuous function is better than discontinuous function to eliminate the chattering. Furthermore, compared with conventional compensation, an adaptive quasi-SMC compensation without any accurate detection for internal parameters is easier to be implementated, which has shown a superior advance. Theoretical analysis and experiments are carried out to validate the correctness of the novel control scheme.

Abstract The concept, state of the art, and future development directions of hybrid semiconductor integrated circuits (HySICs), which combine RF-CMOS ICs with compound semiconductor monolithic microwave integrated circuits (MMICs) are described in this paper, taking up recent wireless technologies as example applications. It is shown that ICs with superior function can be designed by mixing the optimal characteristics from the different semiconductors. To realize new semiconductor ICs, several component technologies for RF-HySIC are introduced in terms of chip/MMIC design, measurement, and breadboard model fabrication. A prototype RF-HySIC is described for the combination of a GaN Schottky barrier diode with a Si RF-IC matching network developed at 5.8GHz. A GaN diode structure, measurement and characterization of nonlinear devices, a GaN amplifier, and a GaAs MMIC are introduced as component technologies. In addition, the design for using an RF-CMOS matching network circuit with a size of 1.2mm × 2.3mm and room-temperature chip/wafer direct bonding under high-pressure conditions are explained. For advanced and autonomous ICs, HySIC and chip/MMIC topologies combined with a processor are proposed for application of HySIC to wireless sensor systems.

This paper proposes an analytical, closed-form AC-DC voltage multiplier model and investigates the dependency of output current and input power on circuit and device parameters. The model uses no fitting parameters and a frequency term applicable to both multipliers using diodes and metal-oxide semiconductor field effect transistors (MOSFETs). Analysis enables circuit designers to estimate circuit parameters, such as the number of stages and capacitance per stages, and device parameters such as saturation current (in the case of diodes) or transconductance (in the case of MOSFETs). Comparisons of the proposed model with SPICE simulation results as well as other models are also provided for validation. In addition, design optimizations and the impact of AC power source impedance on output power are also investigated.

In this paper, a new single soft switched forward converter with a self driven synchronous rectification (SDSR) is introduced. In the proposed converter, a soft switching condition (ZCS turn on and ZVS turn off) is provided for the switch, by an auxiliary circuit without any extra switch. In additional, this auxiliary circuit does not impose high voltage or current stresses on the converter. Since the proposed converter uses SDSR to reduce conductive loss of output rectifier, the rectifier switches are switched under soft switching condition. So, the conductive and switching losses on the converter reduce considerably. Also, implementing control circuit of this converter is very simple, due to the self-driven method employed in driving synchronous rectification and the converter is controlled by pulse width modulation (PWM). The experimental results of the proposed converter are presented to confirm the theoretical analysis.

This work addresses two key topics in the field of energy harvesting and wireless power transfer. The first is the optimum signal design for improved RF-DC conversion efficiency in rectifier circuits by using time varying envelope signals. The second is the design of rectifiers that present reduced sensitivity to input power and output load variations by introducing resistance compression network (RCN) structures.

Efficiency of the photovoltaic-assisted UHF CMOS rectifier, which is one example realization of the synergistic ambient energy harvesting concept, has been improved by symmetric PV cell structure. Balanced biasing for the n-channel and p-channel diode-connected MOSFETs realized by the symmetric PV cells effectively compensates Vths and prevents useless leakage current, resulting in the improved efficiency of the rectifier under low input power conditions. In addition, by extending the balanced biasing concept, output-voltage-boosted PV cell structure was proposed and found to be effective for further improving the efficiency of the rectifier. As a result, under a typical indoor lighting condition of 300lx, power conversion efficiency of 25.4% was achieved at -20dBm of 920MHz RF input and 47kΩ output loading conditions, being 3.6 times larger than a conventional rectifier without PV assistance.

A two-dimensional (2D) wireless power transmission (WPT) system that handles a wide range of transmitted and received power is proposed and evaluated. A transmitter outputs the power to an arbitrary position on a 2D waveguide sheet by using a beam-forming technique. The 2D waveguide sheet does not require an absorber on its edge. The minimum propagation power on the sheet is increased 18 times by using the beam-forming technique. Power amplifier (PA) efficiency was improved from 19% to 46% when the output power was 10dB smaller than peak power due to the use of a PA supply-voltage and input power control method. Peak PA efficiency was 60%. A receiver inputs a wide range of power levels and drives various load impedances with a parallel rectifier. This rectifier enables a number of rectifying units to be tuned dynamically. The rectifier efficiency was improved 1.5 times while input power range was expanded by 6dB and the load-impedance range was expanded fourfold. The rectifier efficiency was 66-73% over an input power range of 18-36dBm at load impedances of 100 and 400Ω.

A photovoltaic (PV)-assisted CMOS rectifier was developed for efficient energy harvesting from ambient radio waves as one example of the synergistic energy harvesting concept. The rectifier operates truly synergistically. A pn junction diode acting as a PV cell converts light energy to DC bias voltage, which compensates the threshold voltage (Vth) of the MOSFETs and enhances the radio frequency (RF) to DC power conversion efficiency (PCE) of the rectifier even under extremely low input power conditions. The indoor illuminance level was sufficient to generate gate bias voltages to compensate Vths. Although the same PV cell structure for biasing nMOS and pMOS transistors was used, photo-generated bias voltages were found to become unbalanced due to the two-layered pn junction structures and parasitic bipolar transistor action. Under typical indoor lighting conditions, a fabricated PV-assisted rectifier achieved a PCE greater than 20% at an RF input power of -20dBm, a frequency of 920MHz, and an output load of 47kΩ. This PCE value is twice the value obtained by a conventional rectifier without PV assistance. In addition, it was experimentally revealed that if symmetric biasing voltages for nMOS and pMOS transistors were available, the PCE would increase even further.

In this paper, a wide input range CMOS multi-mode active rectifier is presented for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the mode of the multi-mode rectifier is automatically selected by switches among the original rectifier mode, 1-stage voltage multiplier mode, and 2-stage voltage multiplier mode. In the original rectifier, the range of the rectified output DC voltage is from 9 V to 19 V for an input AC voltage from 10 V to 20 V. In the multi-mode rectifier, the input-range is wider compared to the original rectifier by 5 V. As a result, the rectified output DC voltage ranges from 7.5 V to 19 V for an input AC voltage from 5 V to 20 V. The proposed multi-mode rectifier is fabricated in a 0.35 µm CMOS process with an active area of around 2500 µm 1750 µm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency is about 94%.