Self-aligned aluminum-gate MOSFET's have been successfully fabricated by employing ultraclean ion implantation technology. The use of ultra high vacuum ion implanter and the suppression of high-energy ion-beam-induced metal sputter contamination have enabled us to form ultra-shallow low-leakage pn junctions by furnace annealing at a temperature as low as 450. The fabricated aluminum-gate MOSFET's have exhibited good electrical characteristics, thus demonstrating a large potential for application to realizing ultra-high-speed integrated circuits.

Precise interconnect analysis is strongly required for giga-scale integration the operation frequency of which is excess 10 GHz. In this study, detailed and accurate analyses of a coaxial interconnect and an actual rectangular interconnect have been performed by the direct evaluation of Maxwell's equations and the finite element method, respectively. It has been revealed that there are two propagation modes for LSI interconnects: skin depth limited propagation mode and interconnect induced slow wave mode. In a miniaturized interconnect, the propagation mode is the interconnect induced slow wave mode; therefore, we cannot obtain the light-speed propagation due to such an interconnect-induced effect. In order to overcome this speed limitation or to improve signal integrity, it is essential to introduce a short interconnect for a miniaturized structure, and a much larger interconnect than the skin depth. We propose a gas-isolated interconnect as a candidate for an ultimately low-k structure in order to increase the signal-propagation speed. By the introduction of such structures, the performance of miniaturized devices in the deep submicron region will be effectively enhanced.

A fast winner search method based on separating all codewords in the original codebook completely into a promising group and an impossible group is proposed. Group separation is realized by using sorted both L1 and L2 norms independently. As a result, the necessary search scope that guarantees full search equivalent PSNR can be limited to the common part of the 2 individual promising groups. The high search efficiency is confirmed by experimental results.

Efficiency of the photovoltaic-assisted UHF CMOS rectifier, which is one example realization of the synergistic ambient energy harvesting concept, has been improved by symmetric PV cell structure. Balanced biasing for the n-channel and p-channel diode-connected MOSFETs realized by the symmetric PV cells effectively compensates Vths and prevents useless leakage current, resulting in the improved efficiency of the rectifier under low input power conditions. In addition, by extending the balanced biasing concept, output-voltage-boosted PV cell structure was proposed and found to be effective for further improving the efficiency of the rectifier. As a result, under a typical indoor lighting condition of 300lx, power conversion efficiency of 25.4% was achieved at -20dBm of 920MHz RF input and 47kΩ output loading conditions, being 3.6 times larger than a conventional rectifier without PV assistance.

In order to reduce the ever increasing cost for ULSI manufacturing due to the complexity of integrated circuits, dramatic simplification in the logic LSI architecture as well as the very flexible circuit configuration have been achieved using a highfunctionality device neuron-MOSFET (γMOS).In γMOS logic circuits, however, computations based on the multiple-valued logic is the key for enhancing the functionality. Therefore, much higher accuracy of processing is required. After brief description of the operational principle of γMOS logic, the relationship between the number of multiple logic levels and the functionality enhancement is discussed for further enhancing the functionality of γMOS logic circuits by increasing the number of multiple logic levels, and the accuracy requirements for the manufacturing processes are studied. The order of a few percent accuracy is required for all principal device structural parameters when it is aimed to handle 50-level multiple-valued variable in the γMOS logic circuit.

Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.

The structure of the nanograting channel MOSFET was optimized by simply rounding the corners of the nanogratings. The current drivabilities of the optimized nanograting channel MOSFETs were enhanced by about 20% and 50% for both n-channel and p-channel MOSFETs, respectively. The mobility changes were analyzed on the basis of channel stress as well as theoretical change of mobilities by various surface orientations. The internal compressive stress of 0.23% was measured in the channel. By suppressing the electric field increase at the corner edge of the nanograting channel to less than 10%, the fabricated rounded nanograting MOSFETs achieved lifetimes of NBTI and TDDB as long as those of conventional planar devices.

Vector quantization (VQ) features a very heavy encoding process. In previous work, an efficient encoding algorithm using mean pyramid has been developed. To improve it further, a fast search algorithm is proposed in this letter. Specifically speaking, four major modifications are made. First, to rearrange the original codebook directly along the sorted real sums to reduce the search scope and then update the lower and upper bound dynamically. Second, to use sum instead of the mean that includes roundoff error to thoroughly avoid a possible mismatched winner. Third, to construct a sum pyramid using 2-pixel-merging other than 4-pixel-merging way to generate more in-between levels. Fourth, to introduce the Cauchy-Schwarz inequality to bridge Euclidean and Manhattan distance together so that the difference check between 2 vectors can be pre-conducted only by much lighter Manhattan distance computation. Experimental results show that the proposed algorithm is more search-efficient.

Drivability-improved MOSFETs were successfully fabricated by using nano-grating silicon wafers. There was almost no additional process change in device fabrication when the height of the gratings was less than the conventional macroscopic wafer surface roughness. The MOSFETs with the grating height of 35 nm showed 21% improvement in current drivability compared to the conventional one with the same device occupancy area. And the roll-off characteristic of threshold voltage of nano-grating device held the line of conventional one in despite of the 3-D channel structure. The technology provides great advantages for drivability improvement without paying much tradeoff of process cost. This proposal will be useful to CMOS-LSIs with high performance in general.

A fast winner search method for VQ based on 2-pixel-merging sum pyramid is proposed in order to reject a codeword at an earlier stage to reduce the computational burden. The necessary search scope of promising codewords is meanwhile narrowed by using sorted real sums. The high search efficiency is confirmed by experimental results.

The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multi-datapath radix-23 computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.82.8 mm2 with CMOS 0.35 µm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensonal FFT in 23.2 µsec and a 2-dimensional one in only 23.8 msec at 133 MHz operation. The power consumption of this processor is 439.6 mW at 3.3 V, 100 MHz operation.

A high-efficiency CMOS rectifier circuit for UHF RFID applications was developed. The rectifier utilizes a self-Vth-cancellation (SVC) scheme in which the threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated from the output voltage of the rectifier itself. A very simple circuit configuration and zero power dissipation characteristics in biasing enable excellent power conversion efficiency (PCE), especially under small RF input power conditions. At higher RF input power conditions, the PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. The proposed SVC CMOS rectifier was fabricated with a 0.35-µm CMOS process and the measured performance was compared with those of conventional nMOS, pMOS, and CMOS rectifiers and other types of Vth cancellation rectifiers as well. The SVC CMOS rectifier achieves 32% of PCE at the -10 dBm RF input power condition. This PCE is larger than rectifiers reported to date under this condition.

The encoding process of vector quantization (VQ) is a time bottleneck preventing its practical applications. In order to speed up VQ encoding, it is very effective to use lower dimensional features of a vector to estimate how large the Euclidean distance between the input vector and a candidate codeword could be so as to reject most unlikely codewords. The three popular statistical features of the average or the mean, the variance, and L2 norm of a vector have already been adopted in the previous works individually. Recently, these three statistical features were combined together to derive a sequential EEENNS search method in [6], which is very efficient but still has obvious computational redundancy. This Letter aims at giving a mathematical analysis on the results of EEENNS method further and pointing out that it is actually unnecessary to use L2 norm feature anymore in fast VQ encoding if the mean and the variance are used simultaneously as proposed in IEENNS method. In other words, L2 norm feature is redundant for a rejection test in fast VQ encoding. Experimental results demonstrated an approximate 10-20% reduction of the total computational cost for various detailed images in the case of not using L2 norm feature so that it confirmed the correctness of the mathematical analysis.

A photovoltaic (PV)-assisted CMOS rectifier was developed for efficient energy harvesting from ambient radio waves as one example of the synergistic energy harvesting concept. The rectifier operates truly synergistically. A pn junction diode acting as a PV cell converts light energy to DC bias voltage, which compensates the threshold voltage (Vth) of the MOSFETs and enhances the radio frequency (RF) to DC power conversion efficiency (PCE) of the rectifier even under extremely low input power conditions. The indoor illuminance level was sufficient to generate gate bias voltages to compensate Vths. Although the same PV cell structure for biasing nMOS and pMOS transistors was used, photo-generated bias voltages were found to become unbalanced due to the two-layered pn junction structures and parasitic bipolar transistor action. Under typical indoor lighting conditions, a fabricated PV-assisted rectifier achieved a PCE greater than 20% at an RF input power of -20dBm, a frequency of 920MHz, and an output load of 47kΩ. This PCE value is twice the value obtained by a conventional rectifier without PV assistance. In addition, it was experimentally revealed that if symmetric biasing voltages for nMOS and pMOS transistors were available, the PCE would increase even further.

Conventional vector quantization (VQ) encoding method by full search (FS) is very heavy computationally but it can reach the best PSNR. In order to speed up the encoding process, many fast search methods have been developed. Base on the concept of multi-resolutions, the FS equivalent fast search methods using mean-type pyramid data structure have been proposed already in. In this Letter, an enhanced sum pyramid data structure is suggested to improve search efficiency further, which benefits from (1) exact computing in integer form, (2) one more 2-dimensional new resolution and (3) an optimal pair selecting way for constructing the new resolution. Experimental results show that a lot of codewords can be rejected efficiently by using this added new resolution that features lower dimensions and earlier difference check order.