IEICE TRANSACTIONS on Electronics
Characteristics of Nano-Grating N-Channel MOSFETs for Improved Current Drivability
Summary :
Drivability-improved MOSFETs were successfully fabricated by using nano-grating silicon wafers. There was almost no additional process change in device fabrication when the height of the gratings was less than the conventional macroscopic wafer surface roughness. The MOSFETs with the grating height of 35 nm showed 21% improvement in current drivability compared to the conventional one with the same device occupancy area. And the roll-off characteristic of threshold voltage of nano-grating device held the line of conventional one in despite of the 3-D channel structure. The technology provides great advantages for drivability improvement without paying much tradeoff of process cost. This proposal will be useful to CMOS-LSIs with high performance in general.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.9 pp.1830-1836
- Publication Date
- 2007/09/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.9.1830
- Type of Manuscript
- PAPER
- Category
- Semiconductor Materials and Devices
Authors
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Xiaoli ZHU, Shin-Ichiro KUROKI, Koji KOTANI, Hideharu SHIDO, Masatoshi FUKUDA, Yasuyoshi MISHIMA, Takashi ITO, "Characteristics of Nano-Grating N-Channel MOSFETs for Improved Current Drivability" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 9, pp. 1830-1836, September 2007, doi: 10.1093/ietele/e90-c.9.1830.
Abstract: Drivability-improved MOSFETs were successfully fabricated by using nano-grating silicon wafers. There was almost no additional process change in device fabrication when the height of the gratings was less than the conventional macroscopic wafer surface roughness. The MOSFETs with the grating height of 35 nm showed 21% improvement in current drivability compared to the conventional one with the same device occupancy area. And the roll-off characteristic of threshold voltage of nano-grating device held the line of conventional one in despite of the 3-D channel structure. The technology provides great advantages for drivability improvement without paying much tradeoff of process cost. This proposal will be useful to CMOS-LSIs with high performance in general.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.9.1830/_p
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@ARTICLE{e90-c_9_1830,
author={Xiaoli ZHU, Shin-Ichiro KUROKI, Koji KOTANI, Hideharu SHIDO, Masatoshi FUKUDA, Yasuyoshi MISHIMA, Takashi ITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Characteristics of Nano-Grating N-Channel MOSFETs for Improved Current Drivability},
year={2007},
volume={E90-C},
number={9},
pages={1830-1836},
abstract={Drivability-improved MOSFETs were successfully fabricated by using nano-grating silicon wafers. There was almost no additional process change in device fabrication when the height of the gratings was less than the conventional macroscopic wafer surface roughness. The MOSFETs with the grating height of 35 nm showed 21% improvement in current drivability compared to the conventional one with the same device occupancy area. And the roll-off characteristic of threshold voltage of nano-grating device held the line of conventional one in despite of the 3-D channel structure. The technology provides great advantages for drivability improvement without paying much tradeoff of process cost. This proposal will be useful to CMOS-LSIs with high performance in general.},
keywords={},
doi={10.1093/ietele/e90-c.9.1830},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - Characteristics of Nano-Grating N-Channel MOSFETs for Improved Current Drivability
T2 - IEICE TRANSACTIONS on Electronics
SP - 1830
EP - 1836
AU - Xiaoli ZHU
AU - Shin-Ichiro KUROKI
AU - Koji KOTANI
AU - Hideharu SHIDO
AU - Masatoshi FUKUDA
AU - Yasuyoshi MISHIMA
AU - Takashi ITO
PY - 2007
DO - 10.1093/ietele/e90-c.9.1830
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2007
AB - Drivability-improved MOSFETs were successfully fabricated by using nano-grating silicon wafers. There was almost no additional process change in device fabrication when the height of the gratings was less than the conventional macroscopic wafer surface roughness. The MOSFETs with the grating height of 35 nm showed 21% improvement in current drivability compared to the conventional one with the same device occupancy area. And the roll-off characteristic of threshold voltage of nano-grating device held the line of conventional one in despite of the 3-D channel structure. The technology provides great advantages for drivability improvement without paying much tradeoff of process cost. This proposal will be useful to CMOS-LSIs with high performance in general.
ER -
English
