This paper presents an ultra-low-power class-AB bulk-driven operational transconductance amplifier operating in the subthreshold region. Employing the partial positive feedback in current mirrors, the effective transconductance and output voltage swing are enhanced considerably without additional power consumption and layout area. Both traditional and proposed OTAs are designed and simulated for a 180 nm CMOS process. They dissipate an ultra low power of 192 nW. The proposed OTA features not only a DC gain enhancement of 14 dB but also a slew rate improvement of 200%. In addition, the improved gain leads to a 5.3 times wider unity-gain bandwidth than that of the traditional OTA.

This study proposes a multiple-output differential-input operational transconductance amplifier-C (MODI OTA-C) filter with an impedance scaler to detect cardiac activity. A ladder-type fifth-orderButterworth low-pass filter with a large time constant and low noise is implemented to reduce coefficient sensitivity and address signal distortion. Moreover, linearized MODI OTA structures with reduced transconductance and impedance scaler circuits for noise reduction are used to achieve a wide dynamic range (DR). The OTA-based circuit is operated in the subthreshold region at a supply voltage of 1 V to reduce the power consumption of the wearable device in long-term use. Experimental results of the filter with a bandwidth of 250 Hz reveal that DR is 57.6 dB, and the harmonic distortion components are below -59 dB. The power consumption of the filter, which is fabricated through a TSMC 0.18 µm CMOS process, is lower than 390 nW, and the active area is 0.135 mm2.

In this paper, a highly linear and low noise CMOS active RF tracking filter for a digital TV tuner is presented. The Gm cell of the Gm-C filter is based on a dynamic source degenerated differential pair with an optimized transistor size ratio, thereby providing good linearity and high-frequency operation. The proposed RF tracking filter architecture includes two complementary parallel paths, which provide harmonic rejection in the low band and unwanted signal rejection in the high band. The fabricated tracking filter based on a 0.13 µm CMOS process shows a 48860 MHz tracking range with 30–32 dB 3rd order harmonic rejection, a minimum input referred noise density of 2.4 nV/, and a maximum IIP3 of 0 dBm at 3 dB gain while drawing 39 mA from a 1.2-V supply. The total chip area is 1 mm0.9 mm.

We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter implemented in a 0.18 µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.

This paper presents Q factor analysis for FET oscillators employing distributed-constant elements. We replace the inductor of a lumped constant Colpitts circuit by a shorted microstrip transmission line for high frequency applications. Involving the FET's transconductance and the transmission line's loss due to both conducting metal and dielectric substrate, we deduce the Q factor formula for the entire circuit in the steady oscillation state. We compared the computed results from the oscillator employing an uniform shorted microstrip line with that of the original LC oscillator. For obtaining even higher Q factor, we modify the shape of transmission line into nonuniform, i.e., step-, tapered-, and partially-tapered stubs. Non-uniformity causes some complexity in the impedance analysis. We exploit a piecewise uniform approximation for tapered part of the microstrip stub, and then involve the asymptotic expressions obtained from both stub's impedance and its frequency derivatives into the active Q factor formula. Applying these formulations, we calculate out the value of capacitance for tuning, the necessary FET's transconductance and achievable active Q factor, and then finally explore oscillator performances with a microstrip stub in different shapes and sizes.

In this paper the transfer function of a system with windowed current integration is discussed. This kind of integration is usually used in a sampling mixer and the current is generated by a transconductance amplifier (TA). The parasitic capacitance (Cp) and the output resistance of the TA (Ro,TA) before the sampling mixer heavily affect the performance. Calculations based on a model including the parasitic capacitance and the output resistance of the TA is carried out. Calculation results show that due to the parasitic capacitance, a notch at the sampling frequency appears, which is very harmful because it causes the gain near the sampling frequency to decrease greatly. The output resistance of the TA makes the depth of the notches shallow and decreases the gain near the sampling frequency. To suppress the effect of Cp and Ro,TA, an operational amplifier is introduced in parallel with the sampling capacitance (Cs). Simulation results show that there is a 17 dB gain increase while Cs is 1,pF, gm is 9,mS, N is 8 with a clock rate of 800,MHz.

This work presents a technique to enhance the performance of the conventional PMOS Colpitts VCO circuit. This technique is accomplished by adding an NMOS cross-coupled pair under the traditional differential Colpitts VCO to enhance the oscillator startup condition and its efficiency. The analytics also support this viewpoint and present a device- choosing method to optimize the output power and phase noise. This new VCO can also be applied to realize the QVCO circuit, because the coupling transistors can be placed in parallel, connecting with the transistors in the NMOS cross-coupled pair, to achieve the proper coupling between individual VCOs. To verify the proposed design concept, two prototypes, which are VCO and QVCO operated at 2.4 GHz and fabricated in CMOS 0.25-µm technology, are designed and tested. The measurement results show that the performance of VCO demonstrates a FOM of about 180 dBC/Hz, and the phase noise of QVCO is -116 dBc/Hz at the 1 MHz offset from oscillation frequency.

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Simulation results of a 0.5-V 100-kHz 5th-order Chebyshev filter based on the proposed OTA in a 0.18 µm CMOS process indicate SNR and SFDR of 68 dB and 63 dB (at 50 kHz+55 kHz) respectively. The filter consumes total power consumption of 60 µW.

Drivability-improved MOSFETs were successfully fabricated by using nano-grating silicon wafers. There was almost no additional process change in device fabrication when the height of the gratings was less than the conventional macroscopic wafer surface roughness. The MOSFETs with the grating height of 35 nm showed 21% improvement in current drivability compared to the conventional one with the same device occupancy area. And the roll-off characteristic of threshold voltage of nano-grating device held the line of conventional one in despite of the 3-D channel structure. The technology provides great advantages for drivability improvement without paying much tradeoff of process cost. This proposal will be useful to CMOS-LSIs with high performance in general.

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the resistive tail-biased differential amplifier and the output stage relies upon the feed-forward class AB technique with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Analysis on the achievable peak voltage swing of the OTA when employed in filters is given. Simulation results of a 0.5-V 100-kHz elliptic 5th-order filter based on the OTA's in a 2-V 0.18 µm CMOS process indicate the differential peak voltage as large as 0.42 Vp (84% of the supply voltage) at 1% THD with the SFDR of 60 dB and the total power consumption of 50 µW.

A novel linear transconductor using translinear cells is proposed. It consists of a voltage follower, a resistor, and a current follower. SPICE simulations using an 8 GHz bipolar transistor-array parameter show that the linear transconductor with a transconductance of 1 mS exhibits a linearity error of less than 0.75% over an input voltage range of 1 V for a supply voltage of 2.0 V. The temperature coefficient of the transconductance is less than 124 ppm/. The -3-dB frequency of the transconductance is more than 4.5 GHz. Applying the linear transconductor as a building block, the design of a bandpass filter with center frequency of 85 MHz and Q-factor of 80 is presented.

The correlation between ohmic contact resistivity (ρc) and transconductance (gm) in AlGaN/GaN high-electron-mobility transistors (HEMTs) was investigated. To characterize ρc precisely, we fabricated a circular transmission line model (c-TLM) pattern adjoined to a field-effect transistor (FET) pattern on an HEMT. By measuring ohmic contact resistance and sheet resistance using the adjoined c-TLM, intrinsic transconductance (gm0), which is not influenced by the source resistance, can be estimated. The gm0 thus obtained is between 179 and 206 mS/mm. Then, it became possible to calculate the correlation between gm and (ρc. We found that ρc should be below 10-5 Ωcm2 for the improvement of gm in AlGaN/GaN HEMT when Rsh 400 Ω/.

This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hybrid cascode compensation are about 40 percent greater than those of the conventional cascode compensation. Circuit level simulation results are provided to show the accuracy of the calculated expressions and also the usefulness of the proposed cascode compensation technique.

In this letter, two kinds of MOS operational transconductance amplifiers (OTAs) based on combiners are presented. Each OTA has the following advantages; one of the proposed OTAs (OTA-1) can be operated at low supply voltage and the other OTA (OTA-2) has wide bandwidth. Through HSPICE simulations with a standard 0.35 µm CMOS device parameters, the operation under the supply voltage of 1.5 V for OTA-1 and the -3 dB bandwidth of several gigahertz for OTA-2 are confirmed.

A high-speed transconductance-C-opamp integrator using a current-feedback amplifier is proposed. The integrator has good frequency response compared with a conventional transconductance-C-opamp integrator using a voltage-feedback amplifier. The current-feedback amplifier shifts the second pole of the proposed integrator to the upper frequency. The frequency is proportional to the current gain of the current-feedback amplifier. The proposed integrator can eliminate effects of the parasitics at the output node of the transconductance since the voltage at the node is fixed. One of the circuit examples of the proposed integrator is shown. Its validity is confirmed through HSPICE simulations. The proposed integrator works as predicted up to 260 MHz.

An intermediate frequency (IF) variable gain amplifier (VGA) with exponential gain control for a radio receiver is fabricated in 0.25-µm CMOS technology. The techniques to improve the bandwidth and to reduce temperature dependence of gain are described. The complete VGA is composed of two stages of linearized transconductance VGA and three stages of fixed gain amplifier (FGA). The complete VGA provides a continuous 10 dB to 76.5 dB gain control range, an IIP3 of -11.5 dBm and an NF of 15 dB at 40 MHz.

The rapid down-scaling of minimum feature size in CMOS technologies has boosted the RF performance, thereby opening up the RF application area to CMOS. The concurrent reduction of supply voltage pushes the MOSFETs used in circuit design more and more into the moderate-inversion regime of operation. As a consequence, compact MOS models are needed that are accurate in all operating regimes, including the moderate-inversion regime. Advanced analogue applications require accurate modelling of distortion, capacitances and noise. RF application of MOSFETs require the extension of this accurate modelling up to high frequencies and in addition accurate modelling of impedance levels and power gain. The implications for compact MOS models will be discussed, together with the state-of-the-art in compact MOS modelling. Special attention will be paid to some well-known circuit examples, and the compact model requirements needed for a correct description. Where relevant MOS Model 11 will be used to illustrate the discussion.

This paper presents a novel class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections. To demonstrate the efficiency of the proposed modulator architectures a prototype with HSPICE is implemented. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage is used to implement the fourth order modulator. Simulation results with OSR of 16 give signal to noise plus distortion ratio (SNDR) and dynamic range (DR) of 90-dB and 92.5-dB including the circuit noise in the 1.25-MHz signal bandwidth, respectively. The circuit is implemented in a 0.13-µm standard CMOS technology. It dissipates about 40-mW from a single 1.2-V power supply voltage.

This paper introduces a way to realize high-pass, band-stop and all-pass transfer functions using two-integrator loop structure consisting of loss-less and lossy integrators. The basic circuit configuration is constructed with five Operational Transconductance Amplifiers (OTAs) and two grounded capacitors. It is shown that the circuit can realize their circuit transfer functions by choosing the input terminals, and that the circuit parameters can also be independently set by the transconductance gains with the proportional block. Although the basic circuit configuration has been known, it seems that the feature for realizing the high-pass, the band-stop and the all-pass transfer functions makes the structure more attractive and useful. An example is given together with simulated results by PSPICE.

This paper proposes design of new linear bipolar OTAs using hyperbolic circuits with an intermediate voltage terminal. Four types of the OTAs are presented; two OTAs contain a hyperbolic sine circuit and the other two OTAs employ a hyperbolic cosine circuit. The linear input voltage range of the proposed OTAs is wider than that of the well-known conventional OTA, multi-TANH doublet, while each proposed OTA has advantages, such as low power dissipation, high-frequency characteristics and so on. The results of SPICE simulation show that satisfactory characteristics are obtained.