Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.

In this paper the transfer function of a system with windowed current integration is discussed. This kind of integration is usually used in a sampling mixer and the current is generated by a transconductance amplifier (TA). The parasitic capacitance (Cp) and the output resistance of the TA (Ro,TA) before the sampling mixer heavily affect the performance. Calculations based on a model including the parasitic capacitance and the output resistance of the TA is carried out. Calculation results show that due to the parasitic capacitance, a notch at the sampling frequency appears, which is very harmful because it causes the gain near the sampling frequency to decrease greatly. The output resistance of the TA makes the depth of the notches shallow and decreases the gain near the sampling frequency. To suppress the effect of Cp and Ro,TA, an operational amplifier is introduced in parallel with the sampling capacitance (Cs). Simulation results show that there is a 17 dB gain increase while Cs is 1,pF, gm is 9,mS, N is 8 with a clock rate of 800,MHz.

A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to less than one tenth compared to a system without the feed-forward compensation, by merely employing the feed-forward compensation system. Further more a design example shows that this settling time can be decreased further to less than one fifteenth through design considerations when compared to a speed optimized phase-locked loop design system without direct reference feed-forward compensation.

Analysis of resonance frequency in shorted transmission lines with inserted capacitor has been made. The analysis shows a resonance frequency dependence on capacitance position on a shorted transmission line. Two analysis methods are presented to predict the resonance frequency and understand how the inserted capacitor affects the resonance frequency of the shorted transmission line. Using this knowledge we propose a new structure for digital controlled oscillators utilizing the capacitance's sensitivity dependence on position of the shorted transmission line to increase the frequency resolution. A 9 GHz transmission line based digital controlled oscillator was designed and fabricated as a proof of concept. Measured results show that more than 100 times frequency step resolution increase is possible utilizing the same tuning capacitor size located at different points on the transmission line.