Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis
Summary :
The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.7 pp.924-930
- Publication Date
- 1997/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
- Category
- Novel Concept Devices
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Ho-Yup KWON, Koji KOTANI, Tadashi SHIBATA, Tadahiro OHMI, "Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 7, pp. 924-930, July 1997, doi: .
Abstract: The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_7_924/_p
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@ARTICLE{e80-c_7_924,
author={Ho-Yup KWON, Koji KOTANI, Tadashi SHIBATA, Tadahiro OHMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis},
year={1997},
volume={E80-C},
number={7},
pages={924-930},
abstract={The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis
T2 - IEICE TRANSACTIONS on Electronics
SP - 924
EP - 930
AU - Ho-Yup KWON
AU - Koji KOTANI
AU - Tadashi SHIBATA
AU - Tadahiro OHMI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1997
AB - The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.
ER -
English
