Fast switching speed, low power consumption, and good stability are some of the important properties of spin transfer torque assisted voltage controlled magnetic anisotropy magnetic tunnel junction (STT-assisted VCMA-MTJ) which makes the non-volatile full adder (NV-FA) based on it attractive for Internet of Things. However, the effects of process variations on the performances of STT-assisted VCMA-MTJ and NV-FA will be more and more obvious with the downscaling of STT-assisted VCMA-MTJ and the improvement of chip integration. In this paper, a more accurate electrical model of STT-assisted VCMA-MTJ is established on the basis of the magnetization dynamics and the process variations in film growth process and etching process. In particular, the write voltage is reduced to 0.7 V as the film thickness is reduced to 0.9 nm. The effects of free layer thickness variation (γtf) and oxide layer thickness variation (γtox) on the state switching as well as the effect of tunnel magnetoresistance ratio variation (β) on the sensing margin (SM) are studied in detail. Considering that the above process variations follow Gaussian distribution, Monte Carlo simulation is used to study the effects of the process variations on the writing and output operations of NV-FA. The result shows that the state of STT-assisted VCMA-MTJ can be switched under -0.3%≤γtf≤6% or -23%≤γtox≤0.2%. SM is reduced by 16.0% with β increases from 0 to 30%. The error rates of writing ‘0’ in the NV-FA can be reduced by increasing Vb1 or increasing positive Vb2. The error rates of writing ‘1’ can be reduced by increasing Vb1 or decreasing negative Vb2. The reduction of the output error rates can be realized effectively by increasing the driving voltage (Vdd).

The unique characteristic of Ternary ripple-carry addition enables us to optimize Ternary Full Adder for this specific application. Carbon nanotube field effect transistors are used in this paper to design new Ternary Half and Full Adders, which are essential components of Ternary ripple-carry adder. The novel designs take the sum of input variables as a single input signal, and generate outputs in a way which is far more efficient than the previously presented similar structures. The new ripple-carry adder operates rapidly, with high performance, and low-transistor-count.

This paper presents symmetric and full swing designs of multiplier and full adder cells, based on weighted inputs for nanotechnology. Carbon Nanotube Field Effect Transistors (CNTFETs) are used to implement the circuits. Proposed designs are simulated using the HSPICE simulation tool and they are compared with their counterparts in terms of delay, power consumption and power-delay product. Significant improvements have been achieved at different voltage levels and different frequencies, load capacitors and temperatures have also been tested. Finally, process variation issue has been analyzed and the results have been reported.

The reduction in the gate length of the current devices to 65 nm causes their I-V characteristics to depart from the traditional MOSFETs. As a result, manufacturing of new efficient devices in nanoscale is inevitable. The fundamental properties of the metallic and semi-conducting carbon Nanotubes (CNTs) make them alternatives to the conventional silicon-based devices. In this paper an ultra high-speed and energy-efficient full adder is proposed, using Carbon Nanotube Field Effect Transistor (CNFET) in nanoscale. Extensive simulation results using HSPICE are reported to show that the proposed adder consumes lower power, and is faster compared to the previous adders.

Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.

A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.

Novel memory and several logic circuits utilizing the chaotic oscillations produced in SQUIDs are proposed. First, the oscillation modes that can be produced in a SQUID circuit are analyzed. The results of simulation for the SQUID show that there exist four types of oscillations: periodic, subharmonic, chaotic and relaxation oscillations. The bifurcation diagram of oscillation waveforms reveals that the hysteresis phenomena in the relation between the terminal voltage or the current and the external flux appear and that these phenomena can be used for a memory operation. Secondary, novel digital circuits such as memory, Exclusive-OR and full adder circuits are proposed by utilizing the chaotic oscillations. In these digital circuits the chaotic oscillations are made correspond to the logic "1," while the periodic and subharmonic oscillations are made to the logic "0." In order to investigate how these digital circuits perform their functions, computer simulations are made. The simulation results show that the right operations can be achieved.

The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.