Voltage-Mode Multiple-Valued Logic Adder Circuits
Summary :
Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E87-C No.6 pp.1054-1061
- Publication Date
- 2004/06/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Ioannis M. THOIDIS, Dimitrios SOUDRIS, Adonios THANAILAKIS, "Voltage-Mode Multiple-Valued Logic Adder Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 6, pp. 1054-1061, June 2004, doi: .
Abstract: Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_6_1054/_p
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@ARTICLE{e87-c_6_1054,
author={Ioannis M. THOIDIS, Dimitrios SOUDRIS, Adonios THANAILAKIS, },
journal={IEICE TRANSACTIONS on Electronics},
title={Voltage-Mode Multiple-Valued Logic Adder Circuits},
year={2004},
volume={E87-C},
number={6},
pages={1054-1061},
abstract={Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Voltage-Mode Multiple-Valued Logic Adder Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1054
EP - 1061
AU - Ioannis M. THOIDIS
AU - Dimitrios SOUDRIS
AU - Adonios THANAILAKIS
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2004
AB - Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.
ER -
English
