In this work, a measurement-based procedure aimed at deriving a behavioral model of Bulk Current Injection (BCI) probes clamped onto multi-wire cable bundles is proposed. The procedure utilizes the measurement data obtained by mounting the probe onto the calibration jig for model-parameters extraction, and 2D electromagnetic simulations to adapt such parameters to the specific characteristics of the cable bundle under analysis. Outcome of the analysis is a behavioral model which can be easily implemented into the SPICE environment. Without loss of generality, the proposed model is here used to predict the radio-frequency noise stressing the terminal units of a two-wire harness. Model accuracy in predicting the common and differential mode voltages induced by BCI at the line terminals is assessed by EM modeling and simulation of the involved injection setup by the commercial software CST Microwave Studio.

This paper investigates the design curves of the class DE amplifier with the nonlinear shunt capacitances for any output Q and any grading coefficient m of the diode junction in the MOSFET. The design curves are derived by the numerical calculation using Spice. The results of this paper have two important meanings. Firstly, it is clarified that the nonlinearities of the shunt capacitances affect the design curves of the class DE amplifier, especially, for low output Q. Moreover, the supply voltage is a quite important parameter to design the class DE amplifier with the nonlinear shunt capacitances. Secondly, it is also clarified that the numerical design tool using Spice, which is proposed by authors, can be applied to the derivation of the design curves. This shows the possibility of the algorithm to be a powerful tool for the analysis of the class E switching circuits. The waveforms from Spice simulations denote the validity of the design curves.

This paper investigates the design curves of class E amplifier with nonlinear capacitance for any output Q and finite dc-feed inductance. The important results are; 1) the capacitance nonlinearity strongly affects the design parameters for low Q, 2) the value of dc-feed inductance is hardly affected by the capacitance nonlinearity, and 3) the input voltage is an important parameter to design class E amplifier with nonlinear capacitance. By carrying out PSpice simulations, we show that the simulated results agree with the desired ones quantitatively. It is expected that the design curves in this paper are useful guidelines for the design of class E amplifier with nonlinear capacitance.

This paper proposes a PCB plane model for generic circuit simulators (SPICE). The proposed model reflects two frequency-dependent losses, namely, skin and dielectric losses. Once power/ground plane pair is divided into arrays of unit-cells, each unit-cell is modeled using a transmission line and the loss model. The loss model is composed of a resistor for DC loss, series RL ladder circuit for skin loss and series RC ladder circuit for dielectric loss. To verify the validity of the proposed model, it is compared with SPICE ac analysis using frequency-dependent resistors. Also, we show that the estimation results using the proposed model have a good correlation with that of VNA measurement for the typical PCB stack-up structure of general desktop PCs. With the proposed model, not only ac analysis but also transient analysis can be easily done for circuits including various non-linear/linear devices since the model consists of passive elements only.

Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.

A neuron MOS transistor has a floating gate and multiple input gates which are capacitively coupling with the floating gate. Dramatic reduction in the number of transistors and interconnections was achieved by employing the neuron MOS in circuit designs. Since the neuron MOS gate electrode is electrically floating, it is not necessarily easy to calculate the floating gate potential using circuit simulator SPICE. In order to simulate floating gate neuron MOS circuits, a macromodel which calculates the floating gate potential combining resistances and dependent voltage and current sources has been proposed. Eight kinds of neuron MOS circuits were designed and fabricated by a double polysilicon two level metal 1.2 µ m CMOS process. Utilizing SPICE, all the neuron MOS circuits were confirmed to operate correctly. The apparent threshold voltage as seen from the input gate in the 2-input n-channel neuron MOS transistor is arbitrarily changed by a control gate signal. Multi-input neuron MOS inverters and neuron MOS full adder circuits have been successfully simulated. Moreover, the effectiveness of the proposed macromodel has been experimentally verified by fabricated circuit measurements. Measured results confirmed that 3-input neuron MOS inverter outputs the low level when the number of input gates to which a high level is applied is more than half of all input gates.