An alternative approach to increasing the functional capability of an integrated circuit chip other than the conventional scaling approach is presented and discussed. We will show the functional enhancement at a very elementary device level is essential in implementing intelligent functions at a system level. The concept of a four-terminal device is reviewed as a guiding principle in considering the device functionality enhancement. As an example of a four-terminal device, the neuron MOS transistor is presented. Applications of neuron MOS transistors to several new architecture circuits are demonstrated and the possibility of implementing intelligent functions directly on integrated circuit hardware is discussed.

This paper describes a guiding principle for designing functional single-electron tunneling (SET) circuitsthat is a way to elicit the potential functions of a given SET circuit by using as a guiding tool the SET circuit stability diagram. A stability diagram is a map that depicts the stable regions of a SET circuit based on the circuit's variable coordinates. By scrutinizing the diagram, we can infer all the potential functions that can be obtained from a circuit configuration. As an example, we take up a well-known SET-inverter circuit and uncover its latent functions by studying the circuit configuration, based on its stability diagram. We can produce various functions, e.g., step-inverter, Schmidt-trigger, memory cell, literal, and stochastic-neuron functions. The last function makes good use of the inherent stochastic nature of single-electron tunneling, and can be applied to Boltzmann-machine neural network systems.

We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.

This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

New functional surface tunnel transistors (STTs) with multiple interband-tunnel-junctions in a symmetric source-to-drain structure are proposed to reduce the number of fabrication steps and to increase functionality. These devices have p⁺/n⁺ interband tunnel junctions in series between a p⁺ source and a p⁺ drain through n⁺ channels. We successfully fabricated GaAs-based multiple-junction STTs (MJ-STTs) using molecular-beam epitaxy regrowth. This fabrication method eliminates the need for two of the photo-masks in the conventional process for asymmetric planar STTs. In the preliminary experiments using multiple-junction p⁺/n⁺ diodes, we found that the peak-voltage increment in negative-differential-resistance (NDR) characteristics due to the reverse-biased tunnel junction in negligible, while the first-peak voltage is roughly proportional to the number of forward-biased tunnel junctions. Moreover, the number of NDR characteristics are completely determined by the number of tunnel junctions. The fabricated STTs with multiple junctions, up to eight junctions, exhibited clear transistor operation with multiple NDR characteristics, which were symmetric with the drain bias. These results indicate that any number of gate-controlled NDR characteristics can be realized in MJ-STTs by using an appropriate number of tunnel junctions in series. In addition, as an example of a functional circuit using MJ-STTs, we implemented a tri-stable circuit with a four-junction STT and a load resistor connected in series. The tri-stable operation was confirmed by applying a combination of a reset pulse and a set pulse for each stable point.

The performances of an SET required for integration are discussed. Conventional SETs had several problems such as large leakage current, insufficient voltage gain and so on. To overcome these problems, a new SET utilizing Schottky barriers as tunnel junctions is proposed. Its current characteristics and Coulomb-blockade conditions are calculated and the effectiveness for an integrated device is discussed.

This paper discusses the features of SOI/CMOS circuits in comparison with bulk/CMOS circuits. We have to design circuits with small fan outs and short wires to take advantage of high-speed and low-power SOI/CMOS devices to their fullest. We can take advantage of the SOI/CMOS structure if the ratio of the source/drain capacitances to the gate capacitances is much greater in the load capacitance. Thus, we propose a new flip-flop circuit with a smaller gate capacitance. The flip-flop circuit operates 30% faster than the previous circuit at 2.0 V. We also propose a buffer circuit having less delay disparity between the complementary output signals. The buffer circuit has the delay disparity of 18 ps at 0.2 pF and 2.0 V. We fabricated an 8-bit frequency divider and a 4-bit demultiplexer using the proposed circuits and 0.35 µm SOI/CMOS process. The 8-bit frequency divider and the 4-bit demultiplexer operate at 2.8 GHz and 1.6 GHz, respectively, at 2.0 V.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.

We have constructed a new concept device with combination of ferroelectric and ferromagnetic materials by a laser ablation technique. An ideal hetero-epitaxy can be obtained owing to the similar crystal structure of perovskite type ferroelectric Pb (Zr, Ti) O₃; (so called PZT) and ferromagnetic (La, Sr) MnO₃. The ferromagnetic (La, Sr) MnO₃ compounds are well known for their colossal magnetoresistance (CMR) properties. The CMR effect is strongly affected by the lattice stress. The PZT, on the other hand, is famous for its large piezoelectrics. We can introduce the lattice stress easily by applying voltage for the piezoelectric compounds. In the heterostructured ferromagnetic/ferroelectric devices, there are remarkable interesting phenomena. Electric properties of the ferromagnetic material can be controlled by piezoelectric effect via distortion of crystal structure.

The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

A suggestion for creating an excitable/oscillatory field with solid-state material is proposed. In essence, the idea is to make a spatial array of "mesoscopic particles" with the characteristics of a first-order phase transition. A theoretical computation shows that an auto-wave, or excitable wave, is generated in such an excitable field. A simple example of using this system as a diode in information flow is given.

This paper explores the potential of multiwave interconnectionsoptical interconnections that employ wavelength components as multiplexable information carriersfor constructing next-generation multiprocessor systems using MCM technology. A hypercube-based multiprocessor network called the multiwave hypercube (MWHC) is proposed, where multiwave interconnections provide highly-flexible dynamic communication channels among processing elements. A performance analysis shows that the use of multiwavelength optics makes possible the reduction of network complexity on an MCM substrate, while supporting low-latency message routing.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

This paper presents a 4-valued content-addressable memory (CAM) for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal is essential to perform a multiple-valued template-matching operation. It is decomposed of a pair of a threshold operation in a CAM cell and a logic-value conversion shared by CAM cells in the same column of a CAM cellular array, which makes a CAM cell function simple. Since a threshold operation together with a 4-valued storage element can be designed by using a single floating-gate MOS transistor, a high-density 4-valued universal-literal CAM with a single-transistor cell can be implemented by using a multi-layer interconnection technology. It is demonstrated that the performance of the proposed CAM is much superior to that of conventional CAMs under the same function.

We propose a new scanning method for image signals using a tree structure of automata. The tree is scanned selectively along the signal path for realizing both lower power consumption and a kind of image compression by skipping nonactive elements. We designed the node automata along with photo-detectors of 3232 in a 7.2 mm7.2 mm chip using a 1.5µm CMOS technology. We demonstrate applications of the tree structure using its feature of selective activation; a moving picture compression using inter-frame difference, an adaptive resolution scan like human eyesight and a motion compensation as examples.

Genetic algorithms were introduced by Holland in 1975 as a method of solving difficult optimization problems by means of simulated evolution. A major drawback of genetic algorithms is their slowness when emulated by software on conventional computers. Described is an adaptation of the original genetic algorithm that is advantageous to hardware implementation along with the architecture of a hardware framework that performs the functions of population storage, selection, crossover, mutation, fitness evaluation, and survival determination. Programming of the framework is illustrated with the set coverage problem that exhibits a 6,000 speed-up over software emulation on a 100 MHz workstation.

We propose a memory-based processor called a Functional Memory Type Parallel Processor for vector quantization (FMPP-VQ). The FMPP-VQ is intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search on vector quantization. In the nearest neighbor search, we look for a vector nearest to an input one among a large number of code vectors. The FMPP-VQ has as many PEs (processing elements, also called "blocks") as code vectors. Thus distances between an input vector and code vectors are computed simultaneously in every PE. The minimum value of all the distances is searched in parallel, as in conventional CAMs. The computation time does not depend on the number of code vectors. In this paper, we explain the detail of the architecture of the FMPP-VQ, its performance and its layout density. We designed and fabricated an LSI including four PEs. The test results and performance estimation of the LSI are also reported.

A digital neuro chip with proliferating neuron architecture is described. This chip simulates a neural network model called the adaptive segmentation of quantizer neuron architecture (ASQA). It has proliferating neurons, and can automatically form the optimum network structure for recognition according to the input data. To develop inexpensive commercial hardware and implement a proliferating neuron architecture, we adopt a virtual neuron system for hardware implementation. Namely, this chip is implemented with only an arithmetic unit for network computations, and the network information such as network structure, synaptic weights and so on, are stored in external memories. We devise our original architecture which can efficiently memorize the network information, and moreover, construct a structured network using the ASQA model. As a result, we can recognize about 3,000 Kanji characters using a single chip and a recognition speed of 4.6 msec/character is achieved on a PC.

A novel learning algorithm for a neural network LSI which has low resolution synapse weights is proposed. Following a brief discussion of the synapse weight adaptation mechanism in the gradient descent scheme, we propose a way of achieving relaxation from the influence of discretized weight. Restriction of the number of synapses to be updated in one learning iteration is effective to relax the influence. Simulation results support the effectiveness of this learning algorithm. Low resolution synapses will be practical to realize large-scale neural network LSIs.

A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

A sparse memory access architecture which is proposed to achieve a high-computational-speed neural-network LSI is described in detail. This architecture uses two key techniques, compressible synapse-weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neuron calculations without incurring an accuracy penalty. The test chip based on this architecture has 96 parallel data-driven processing units and enough memory for 12,288 synapse weights. In a pattern recognition example, the number of memory accesses and neuron calculations was reduced to 0.87% that needed in the conventional method and the practical performance was 18 GCPS. The sparse memory access architecture is also effective when the synapse weights are stored in off-chip memory.

Spectral transform methods have been widely studied for classification and analysis of logic functions. Spectral methods have also been used for logic synthesis, and by use of BDDs, practical-sized synthesis problems have been solved. Wavelet theory has recently attracted the attention of researchers in the signal processing field. The Haar function is used in both spectral methods and in signal processing to obtain spectral coefficients of logic functions of signals. In this paper spectral transform-based analysis of neural nets verifying signal processing and discrete function is presented. A neural net element is defined as a discrete function with multi-valued input signals and multi-valued or binary outputs. The multi-valued variable is realized as a variable (V, W) formed by a pair of a binary value and a multi-value pulse width. The multi-valued encoding is used with the multi-valued Haar function to give meanings to the wavelet coefficients from the view of Boolean algebra. A design example shows that these conceptually different concepts are closely related.

In this paper a novel narrow-band bandpass filter with an output pair of analytic signals is presented. Since it is based on the complex analog filter, both synthesis and response characteristics of this filter are different from conventional bandpass filters. In the design of this filter, the frequency shift method is employed and the conventional lowpass to bandpass frequency transformation is not required. The analysis and examples show that the output signal pair of the proposed filter possesses same filtering characteristics and a 90 degree phase shifting characteristics in the passband. Therefore, the proposed filter will be used for a single sideband (SSB) signal generator without quadrature generator.

Currently, a typical 5454 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea in the present paper is a power optimization for the data compressors based on a Window Detector. The role of the Window Detector is detecting the input data, activating a selected operation unit, choosing the optimized output data, and driving the next stage. It can reduce the power consumption drastically because only one selected operation unit (a Window) is activated. The power consumption of the proposed data compressors is reduced by about 33%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one. Furthermore, the power consumption dependent on the input data transition is shown for both the static CMOS logic and the nMOS pass transistor logic.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

This paper describes influence of the relaxation current in Ba_xSr_(1-x)TiO₃ (BST) thin films on dynamic random access memory (DRAM) operation. The relaxation current is a transient content of dielectric leakage currents. In BST thin films (expected to be a cell capacitor dielectric in 256 Mb DRAM and beyond), the relaxation current often displays the power law behavior I(t)t^-1. This leads to the singularity near the time zero. When one attempts to evaluate precisely the influence of this leakage on DRAM operation, the behavior should be estimated on a time-dependent bias. However, such a singular behavior makes analysis based on a linear response difficult. In this analysis, we start by assuming that the behavior of the relaxation current can be modeled as a linear equivalent circuit. We also assume that the relaxation current follows the power law, I(t)t^-1 for 1 ns<t<1 s. Then, the voltage drop across the capacitor due to the relaxation current is expressed by a integral equation. The singularity is isolated after the integral equation is transformed. All the parameters in the transformed integral equation are related to finite measured quantities. The transformed equation is solved by iteration, and the problem of the logarithmic divergence is consistently solved. The BST films fabricated in our experiment show an average voltage drop of 7 to 10% during the refresh period of 1 s. This will be a concern for 256 Mb DRAMs and beyond.

The key concept of Physical Optics (PO), originally developed for a perfectly electric conductor (PEC), consists in that the high frequency fields on the scatterer surface are approximated by those which would exist on the infinite flat surface tangent to the scatterer. The scattered fields at arbitrary observation points are then calculated by integrating these fields on the scatterer. This general concept can be extended to arbitrary impedance surfaces. The asymptotic evaluation of this surface integration in terms of diffraction coefficients gives us the fields in analytical forms. In this paper, uniform PO diffraction coefficients for the impedance surfaces are presented and their high accuracy is verified numerically. These coefficients are providing us with the tool for the mechanism extraction of various high frequency methods such as aperture field integration method and Kirchhoff's method.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.

A model for estimating the bending loss of 1.3 µm zero-dispersion single-mode fibers at 1.58 µm from the value at 1.55 µm is investigated experimentally and theoretically. An approximated equation for estimating the bending loss ratio of 1.58 µm to 1.55 µm is proposed, which provides good agreement with the experimental results.