CAM-Based Highly-Parallel Image Processing Hardware

Takeshi OGURA; Mamoru NAKANISHI

CAM-Based Highly-Parallel Image Processing Hardware

Takeshi OGURA, Mamoru NAKANISHI

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This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.7 pp.868-874

Publication Date: 1997/07/25

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)

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Takeshi OGURA, Mamoru NAKANISHI, "CAM-Based Highly-Parallel Image Processing Hardware" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 7, pp. 868-874, July 1997, doi: .
Abstract: This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_7_868/_p

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@ARTICLE{e80-c_7_868,
author={Takeshi OGURA, Mamoru NAKANISHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={CAM-Based Highly-Parallel Image Processing Hardware},
year={1997},
volume={E80-C},
number={7},
pages={868-874},
abstract={This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - CAM-Based Highly-Parallel Image Processing Hardware
T2 - IEICE TRANSACTIONS on Electronics
SP - 868
EP - 874
AU - Takeshi OGURA
AU - Mamoru NAKANISHI
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1997
AB - This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.
ER -