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Minkyu SONG, Kunihiro ASADA, "Power Optimization for Data Compressors Based on a Window Detector in a 5454 Bit Multiplier" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 7, pp. 1016-1024, July 1997, doi: .
Abstract: Currently, a typical 5454 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea in the present paper is a power optimization for the data compressors based on a Window Detector. The role of the Window Detector is detecting the input data, activating a selected operation unit, choosing the optimized output data, and driving the next stage. It can reduce the power consumption drastically because only one selected operation unit (a Window) is activated. The power consumption of the proposed data compressors is reduced by about 33%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one. Furthermore, the power consumption dependent on the input data transition is shown for both the static CMOS logic and the nMOS pass transistor logic.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_7_1016/_p
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@ARTICLE{e80-c_7_1016,
author={Minkyu SONG, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power Optimization for Data Compressors Based on a Window Detector in a 5454 Bit Multiplier},
year={1997},
volume={E80-C},
number={7},
pages={1016-1024},
abstract={Currently, a typical 5454 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea in the present paper is a power optimization for the data compressors based on a Window Detector. The role of the Window Detector is detecting the input data, activating a selected operation unit, choosing the optimized output data, and driving the next stage. It can reduce the power consumption drastically because only one selected operation unit (a Window) is activated. The power consumption of the proposed data compressors is reduced by about 33%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one. Furthermore, the power consumption dependent on the input data transition is shown for both the static CMOS logic and the nMOS pass transistor logic.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Power Optimization for Data Compressors Based on a Window Detector in a 5454 Bit Multiplier
T2 - IEICE TRANSACTIONS on Electronics
SP - 1016
EP - 1024
AU - Minkyu SONG
AU - Kunihiro ASADA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1997
AB - Currently, a typical 5454 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea in the present paper is a power optimization for the data compressors based on a Window Detector. The role of the Window Detector is detecting the input data, activating a selected operation unit, choosing the optimized output data, and driving the next stage. It can reduce the power consumption drastically because only one selected operation unit (a Window) is activated. The power consumption of the proposed data compressors is reduced by about 33%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one. Furthermore, the power consumption dependent on the input data transition is shown for both the static CMOS logic and the nMOS pass transistor logic.
ER -
54 Bit Multiplier
English
