IEICE TRANSACTIONS on Electronics
An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)
Summary :
A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.7 pp.911-917
- Publication Date
- 1997/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
- Category
- Novel Structure Devices
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Tetsuo ENDOH, Tairiku NAKAMURA, Fujio MASUOKA, "An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 7, pp. 911-917, July 1997, doi: .
Abstract: A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_7_911/_p
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@ARTICLE{e80-c_7_911,
author={Tetsuo ENDOH, Tairiku NAKAMURA, Fujio MASUOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)},
year={1997},
volume={E80-C},
number={7},
pages={911-917},
abstract={A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)
T2 - IEICE TRANSACTIONS on Electronics
SP - 911
EP - 917
AU - Tetsuo ENDOH
AU - Tairiku NAKAMURA
AU - Fujio MASUOKA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1997
AB - A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.
ER -
English
