In this study, simulations are performed to design an optimal device for thinning the GaN channel layer on the semi-insulating layer in HEMT. When the gate length is 50nm, the thickness of the undoped channel must be thinner than 300nm to observe the off state. When the GaN channel layer is an Fe-doped, an on/off ratio of ~300 can be achieved even with a gate length of 25nm, although the transconductance is slightly reduced.

A low VDD current mirror with deep sub-micron vertical MOSFETs is presented. The keys are new bias circuits to reduce both the minimum VDD for the operation and the sensitivity of the output current on VDD. In the simulation, our circuits reduce the minimum VDD by about 17% and the VDD sensitivity by one order both from those of the conventional. In the simulation with 90nm φ vertical MOSFET approximate models, our circuit shows about 4MΩ output resistance at 1.2-V VDD with the small temperature dependence, which is about six times as large as that with planar MOSFETs.

In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (Leff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).

An asymmetric Dual Metal Stack Gate (DMSG) SOI MOSFET transistor has been investigated for its enhanced electrical characteristics. A 2-D physical model has been proposed and its results have been confirmed by those obtained by simulation. These results predict better short channel effects such as drain induced barrier lowering (DIBL) characteristics and hot carrier effects for this device compared to those for conventional SOI MOSFETs. The effects of the Stacked Gate (SG) and Dual Metal Gate (DMG) structures on short channel effects are compared. It has been observed that SG reduces DIBL significantly, while DMG prevents the normal roll-off of the threshold voltage reduction.

We have proposed the high-density triangular parallel wire channel MOSFET on an SOI substrate and demonstrated the suppressed short channel effects by simulation and experiment. In this device structure, the fabrication process is fully compatible with the planar MOSFET process and is much less complicated than other non-planer device structures including gate-all-around (GAA) and double-gate SOI MOSFETs. In addition, our fabrication process makes it possible to double the wire density resulting in the higher current drive. The three-dimensional simulation results show that the proposed triangular wire channel MOSFET has better short channel characteristics than single-gate and double-gate SOI MOSFETs. The fabricated triangular parallel wire channel MOSFETs show better subthreshold characteristics and less drain induced barrier lowering (DIBL) than the single-gate SOI MOSFETs.

This paper reports the evaluation results of the channel boron distribution in the deep sub-0.1 [µm] n-MOSFETs for the first time. It has been found that the boron depletion effect becomes dominant and the reverse short channel effect becomes less significant in the deep sub-0.1 [µm] n-MOSFETs. It has been also found that the sheet charge distribution responsible for the reverse short channel effect is localized within a distance of 100 [nm] from the source/drain-extension junction.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.