A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.