A 3.2 GFLOPS Neural Network Accelerator
Summary :
We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.7 pp.859-867
- Publication Date
- 1997/07/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
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Shinji KOMORI, Yutaka ARIMA, Yoshikazu KONDO, Hirono TSUBOTA, Ken-ichi TANAKA, Kazuo KYUMA, "A 3.2 GFLOPS Neural Network Accelerator" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 7, pp. 859-867, July 1997, doi: .
Abstract: We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_7_859/_p
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@ARTICLE{e80-c_7_859,
author={Shinji KOMORI, Yutaka ARIMA, Yoshikazu KONDO, Hirono TSUBOTA, Ken-ichi TANAKA, Kazuo KYUMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 3.2 GFLOPS Neural Network Accelerator},
year={1997},
volume={E80-C},
number={7},
pages={859-867},
abstract={We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - A 3.2 GFLOPS Neural Network Accelerator
T2 - IEICE TRANSACTIONS on Electronics
SP - 859
EP - 867
AU - Shinji KOMORI
AU - Yutaka ARIMA
AU - Yoshikazu KONDO
AU - Hirono TSUBOTA
AU - Ken-ichi TANAKA
AU - Kazuo KYUMA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1997
AB - We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.
ER -
English
