A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 µm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

In this paper we study the evolution of the resonance zones that appear in connection with a Hopf-pitchfork bifurcation exhibited by a Z2-symmetric electronic circuit. These regions, bounded by curves of folds (saddle-node bifurcations) may be closed or open depending on the values of the parameters. An angular degeneracy on the torus bifurcation curve originates the banana shape of Arnold's tongues. The presence of homoclinic bifurcations is also pointed out.

This paper describes the expanded generalized method of characteristics (GMC) in order to handle large linear interconnect networks. The conventional GMC is applied to modeling each of transmission lines. Therefore, this method is not suitable to deal with large linear networks containing many transmission lines. Here, we propose the expanded GMC method to overcome this problem. This method computes a characteristic impedance and a new propagation function of the large linear networks containing many transmission lines. Furthermore the wave propagation delay is removed from the new wave propagation function using delay evaluation technique. Finally, it is shown that the present method enables the efficient and accurate simulation of the transmission line networks.

This paper presents the several bifurcation phenomena generated in nonlinear three-phase circuit with symmetry. The circuit consists of delta-connected nonlinear inductors, capacitors and three-phase symmetrical voltage sources. Particular attention is paid to the subharmonic oscillations of order 1/2. We analyze the bifurcations of the oscillations from both theoretical and experimental points. As a tool of analysis, we use the homotopy method. Additionally, by comparing with single-phase and single-phase-like circuits, the special feature of the three-phase circuit is revealed.

An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

Fractal immittance, expressed by an admittance sa (0<|a|<1), is simulated by the analog circuits composed of finite numbers of conventional elements, resistance R, capacitance C and inductance L, based on the distributed-relaxation-time models. The correlation between the number of R-C or R-L pairs and the optimum pole interval to give the widest bandwidth is estimated for each a-value by the numerical calculation for each circuit against a given criterion with respect to the phase angle. It is found that the bandwidth of 5 decades with a phase-angle error of 1 can be composed for |a|=0.1-0.9 using eighteen pairs or less of the elements.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

A 1.55-µm hybrid integrated wavelength-converter module was fabricated using a two-channel spot-size converter integrated semiconductor optical amplifier (SS-SOA) on a planar-lightwave-circuit (PLC) platform. Clear eye opening and penalty-free wavelength conversion were obtained at 2.5-Gb/s modulation with a wide wavelength difference of 46 nm. The module showed good characteristics including low insertion loss (0.1 dB), and high conversion efficiency (-0.2 dB). It also showed stable wavelength conversion for as wide as a 13 temperature range.

A 1.55-µm hybrid integrated wavelength-converter module was fabricated using a two-channel spot-size converter integrated semiconductor optical amplifier (SS-SOA) on a planar-lightwave-circuit (PLC) platform. Clear eye opening and penalty-free wavelength conversion were obtained at 2.5-Gb/s modulation with a wide wavelength difference of 46 nm. The module showed good characteristics including low insertion loss (0.1 dB), and high conversion efficiency (-0.2 dB). It also showed stable wavelength conversion for as wide as a 13 temperature range.

We propose manifold piecewise constant systems (ab. MPC) and consider basic phenomena: the 2-D, 3-D and 4-D MPCs exhibit limit-cycle, line-expanding chaos and area-expanding chaos, respectively. The righthand side of the state equation is piecewise-constant, hence the system dynamics can be simplified into a piecewise-linear return map which can be expressed explicitly. In order to analyze the piecewise-linear return map, we introduce an evaluation function for the piecewise-linear return map and give theoretical evidence for chaos generation. Also the chaotic behaviors are demonstrated in the laboratory.

A cavity-backed two-element rectangular loop slot antenna for circular polarization is presented and investigated by using the generalized network formulation based on the equivalence principle. By applying the method of moments, the magnetic current including the effect of the cavity is obtained for a thin rectangular loop slot. Two short-circuiting points are introduced on the slots to get circular polarization and symmetrical radiation pattern. The axial ratio bandwidth (3 dB) with VSWR (2) reaches 7.6%. The measured and computed results are in good agreement.

This paper suggests a new type of 180-degree 3 dB hybrid, which consists of a cylindrical cavity and four E-plane rectangular waveguides radially coupled with it, and shows that good hybrid properties are realized by modifying the positions of the four input/output waveguides and the radius of the cylindrical cavity that are determined by the field distribution of the TE111 resonant mode. Moreover, a method of broadening the bandwidth with additional impedance steps is described. The present hybrid is marked by simple structure, and hence is useful for applications at millimeter wave frequencies and to high-power microwave systems. Experimental verification is additionally shown.

Measurement-based mathematical modeling is an attractive approach for simulating, accurately and efficiently, circuits based on active devices from a diverse range of constantly evolving processes and technologies. The principle of the measurement-based approach is that it is often most practical to characterize the device with various high-frequency measurements, and then mathematically transform the data to produce predictive device dynamical models for small-signal (linear) and large-signal (nonlinear) circuit design purposes. There are many mathematical, physical, and measurement considerations, however, that must be incorporated into any sound framework for successful measurement-based modeling. This paper will review some foundations of the subject and discuss some future trends. Review topics include constructing nonlinear constitutive relations from linear data parameterized by operating point and conservation laws including terminal charge conservation and energy conservation. Recent advances and trends will be discussed, such as pulsed I-V and pulsed S-parameter characterization with implications for electro-thermal and dispersive dynamical models, nonlinear wave-form measurements, and the relationship to some black-box behavioral modeling approaches.

A complex modular process flow was developed for PRISM technology to permit increased system integration. In order to combine the required functions--submicron CMOS Logic, Nonvolatile Memories, Precision Linear, and Power Drivers--on a monolithic silicon chip, a highly structured, systematic approach to process synthesis was developed. TCAD tools were used extensively for process design and verification. The 60 V LDMOS power transistor and the Flash memory cell built in the technology will be described to illustrate the process synthesis methodology.

Low-voltage technique for IC is getting one of the most important matters. It is quite difficult to realize a filter which can operate at 1 V or less because the base-emitter voltage of transistors can hardly be reduced. A design of a low-voltage continuous-time filter is presented in this paper. The basic building block of the filter is a pseudo-differential transconductor which has no tail current source. Therefore, the operating voltage is lower than that of an emitter-coupled pair. However, the common-mode (CM) gain of the transconductor is quite high and the CMRR is low. In order to reduce the CM gain, a CM feedback circuit is employed. The transconductance characteristic is expressed as the function of hyperbolic cosine. The designed filter is a fifth-order gyrator-C filter. The transconductor and the filter which has a fifth-order Butterworth lowpass characteristic are demonstrated by PSpice simulation. Transconductance characteristic, CMRR and stability of the transconductor are confirmed through the simulation. In the analysis of the filter, frequency response and offset voltage are examined. It is shown that the filter which has corner frequency of the order of megahertz can operate at a 1 V supply voltage.

In this paper, a new digital chaos circuit which can generate multiple-scroll strange attractors is proposed. Being based on the piecewise-linear function which is determined by on-chip supervised learning, the proposed digital chaos circuit can generate multiple-scroll strange attractors. Hence, the proposed circuit can exhibit various bifurcation phenomena. By numerical simulations, the learning dynamics and the quasi-chaos generation of the proposed digital chaos circuit are analyzed in detail. Furthermore, as a design example of the integrated digital chaos circuit, the proposed circuit realizing the nonlinear function with five breakpoints is implemented onto the FPGA (Field Programmable Gate Array). The synthesized FPGA circuit which can generate n-scroll strange attractors (n=1, 2, 4) showed that the proposed circuit is implementable onto a single FPGA except for the SRAM.

During past decade MOS transistors have been aggressively scaled to dimensions below sub-quarter micron, the so called ultra deep submicron (UDSM) technology. At these dimensions transistor characteristics can not be accurately modeled using classical approach presently used in the most commonly used MOSFET models such as BSIM3, MOS9 etc, without recourse to large number of empirical parameters. In this paper we will discuss short comings of the present models and show how to overcome them using a hybrid approach of modeling, wherein both function regional and surface potential based approaches are combined together, that results in a model that reflects UDSM device behavior with smaller set of physically meaningful, and easily extractable model parameters. Various physical effects that need to be considered for UDSM modeling such as quantization of the inversion layer carrier, mobility degradation, carrier velocity saturation and overshoot, polydepletion effect, bias dependent source/drain resistance, vertical and lateral doping profiles, etc. will be discussed.

In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and 3 dB bandwidth are 9.56 µW and 107 MHz, respectively. The active area of the proposed multiplier is 210 µm 140 µm.