Modeling and Characterization of Ultra Deep Submicron CMOS Devices
Summary :
During past decade MOS transistors have been aggressively scaled to dimensions below sub-quarter micron, the so called ultra deep submicron (UDSM) technology. At these dimensions transistor characteristics can not be accurately modeled using classical approach presently used in the most commonly used MOSFET models such as BSIM3, MOS9 etc, without recourse to large number of empirical parameters. In this paper we will discuss short comings of the present models and show how to overcome them using a hybrid approach of modeling, wherein both function regional and surface potential based approaches are combined together, that results in a model that reflects UDSM device behavior with smaller set of physically meaningful, and easily extractable model parameters. Various physical effects that need to be considered for UDSM modeling such as quantization of the inversion layer carrier, mobility degradation, carrier velocity saturation and overshoot, polydepletion effect, bias dependent source/drain resistance, vertical and lateral doping profiles, etc. will be discussed.
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- IEICE TRANSACTIONS on Electronics Vol.E82-C No.6 pp.967-975
- Publication Date
- 1999/06/25
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- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
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Narain D. ARORA, "Modeling and Characterization of Ultra Deep Submicron CMOS Devices" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 6, pp. 967-975, June 1999, doi: .
Abstract: During past decade MOS transistors have been aggressively scaled to dimensions below sub-quarter micron, the so called ultra deep submicron (UDSM) technology. At these dimensions transistor characteristics can not be accurately modeled using classical approach presently used in the most commonly used MOSFET models such as BSIM3, MOS9 etc, without recourse to large number of empirical parameters. In this paper we will discuss short comings of the present models and show how to overcome them using a hybrid approach of modeling, wherein both function regional and surface potential based approaches are combined together, that results in a model that reflects UDSM device behavior with smaller set of physically meaningful, and easily extractable model parameters. Various physical effects that need to be considered for UDSM modeling such as quantization of the inversion layer carrier, mobility degradation, carrier velocity saturation and overshoot, polydepletion effect, bias dependent source/drain resistance, vertical and lateral doping profiles, etc. will be discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_6_967/_p
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@ARTICLE{e82-c_6_967,
author={Narain D. ARORA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Modeling and Characterization of Ultra Deep Submicron CMOS Devices},
year={1999},
volume={E82-C},
number={6},
pages={967-975},
abstract={During past decade MOS transistors have been aggressively scaled to dimensions below sub-quarter micron, the so called ultra deep submicron (UDSM) technology. At these dimensions transistor characteristics can not be accurately modeled using classical approach presently used in the most commonly used MOSFET models such as BSIM3, MOS9 etc, without recourse to large number of empirical parameters. In this paper we will discuss short comings of the present models and show how to overcome them using a hybrid approach of modeling, wherein both function regional and surface potential based approaches are combined together, that results in a model that reflects UDSM device behavior with smaller set of physically meaningful, and easily extractable model parameters. Various physical effects that need to be considered for UDSM modeling such as quantization of the inversion layer carrier, mobility degradation, carrier velocity saturation and overshoot, polydepletion effect, bias dependent source/drain resistance, vertical and lateral doping profiles, etc. will be discussed.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - Modeling and Characterization of Ultra Deep Submicron CMOS Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 967
EP - 975
AU - Narain D. ARORA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1999
AB - During past decade MOS transistors have been aggressively scaled to dimensions below sub-quarter micron, the so called ultra deep submicron (UDSM) technology. At these dimensions transistor characteristics can not be accurately modeled using classical approach presently used in the most commonly used MOSFET models such as BSIM3, MOS9 etc, without recourse to large number of empirical parameters. In this paper we will discuss short comings of the present models and show how to overcome them using a hybrid approach of modeling, wherein both function regional and surface potential based approaches are combined together, that results in a model that reflects UDSM device behavior with smaller set of physically meaningful, and easily extractable model parameters. Various physical effects that need to be considered for UDSM modeling such as quantization of the inversion layer carrier, mobility degradation, carrier velocity saturation and overshoot, polydepletion effect, bias dependent source/drain resistance, vertical and lateral doping profiles, etc. will be discussed.
ER -
English
