In this paper, we propose a new method for the bias-dependent parameter extraction of a MOSFET, which covers DC to over 100 GHz. The DC MOSFET model provided by the chip foundry is assumed to be correct, and the core DC characteristics are designed to be asymptotically recovered at low frequencies. This is carried out by representing the corrections required at high frequencies using a bias-dependent Y matrix, assuming that a parasitic nonlinear two-port matrix (Y-wrapper) is connected in parallel with the core MOSFET. The Y-wrapper can also handle the nonreciprocity of the parasitic components, that is, the asymmetry of the Y matrix. The reliability of the Y-wrapper model is confirmed through the simulation and measurement of a one-stage common-source amplifier operating at several bias points. This paper will not discuss about non-linearity.

During past decade MOS transistors have been aggressively scaled to dimensions below sub-quarter micron, the so called ultra deep submicron (UDSM) technology. At these dimensions transistor characteristics can not be accurately modeled using classical approach presently used in the most commonly used MOSFET models such as BSIM3, MOS9 etc, without recourse to large number of empirical parameters. In this paper we will discuss short comings of the present models and show how to overcome them using a hybrid approach of modeling, wherein both function regional and surface potential based approaches are combined together, that results in a model that reflects UDSM device behavior with smaller set of physically meaningful, and easily extractable model parameters. Various physical effects that need to be considered for UDSM modeling such as quantization of the inversion layer carrier, mobility degradation, carrier velocity saturation and overshoot, polydepletion effect, bias dependent source/drain resistance, vertical and lateral doping profiles, etc. will be discussed.