In this paper, we propose a new method for the bias-dependent parameter extraction of a MOSFET, which covers DC to over 100 GHz. The DC MOSFET model provided by the chip foundry is assumed to be correct, and the core DC characteristics are designed to be asymptotically recovered at low frequencies. This is carried out by representing the corrections required at high frequencies using a bias-dependent Y matrix, assuming that a parasitic nonlinear two-port matrix (Y-wrapper) is connected in parallel with the core MOSFET. The Y-wrapper can also handle the nonreciprocity of the parasitic components, that is, the asymmetry of the Y matrix. The reliability of the Y-wrapper model is confirmed through the simulation and measurement of a one-stage common-source amplifier operating at several bias points. This paper will not discuss about non-linearity.

The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2 mA and 48.2 mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.

This paper presents a theoretical analysis of a tunable resonator using a coupled line and switches for the first time. The tunable resonator has the capability to tune its resonant frequency and bandwidth. The resonator has two suitable features on its tunable capability. The first feature is that the resonator retains its resonant frequency during bandwidth tuning. The second feature is that the on-state switch for tuning the bandwidth does not affect the insertion loss at the resonant frequency. These features are theoretically confirmed by its mathematically derived input impedance. The results from electromagnetic simulation and measurement of the fabricated tunable resonator also confirm these features. The fabricated tunable resonator changes the resonant frequency from 2.6 GHz to 6.4 GHz and bandwidth between 9% and 55%.

In this article, a new Beamforming Network (BFN) realized in Broadside Coupled Stripline (BCS) is proposed to feed 1×4 and 2×2 arrays antenna at 28 GHZ-Band. The new BFN is composed only of couplers and phase shifters. It doesn't require any crossover compared to the conventional Butler Matrix (BM) which requires two crossovers. The tight coupling and low loss characteristics of the BCS allow a design of a compact and wideband BFN. The new BFN produces the phase differences of (±90°) and (±45°, ±135°) respectively in x- and y-directions. Its integration with a 1×4 linear array antenna reduces the array area by 70% with an improvement of the gain performance compared with the conventional array. The integration with a 2×2 array allows the realization of a full 2-D beam scanning. The proposed concept has been verified experimentally by measuring the fabricated prototypes of the BFN, the 1-D and 2-D patch arrays antennas. The measured 11.5 dBi and 11.3 dBi maximum gains are realized in θ0 = 14° and (θ0, φ0) = (45°,345°) directions respectively for the 1-D and 2-D patch arrays. The physical area of the fabricated BFN is only (0.37λ0×0.3λ0×0.08λ0), while the 1-D array and 2-D array antennas areas without feeding transmission lines are respectively (0.5λ0×2.15λ0×0.08λ0) and (0.9λ0×0.8λ0×0.08λ0).

E-band communication is allocated to the frequency bands of 71-76 and 81-86GHz. Radio-frequency (RF) front-end components for E-band communication have been realized using compound semiconductor technology. To realize a CMOS LNA for E-band communication, we propose a gain-boosted cascode amplifier (GBCA) stage that simultaneously provides high gain and stability. Designing an LNA from scratch requires considerable time because the tuning of matching networks with consideration of the parasitic elements is complicated. In this paper, we model the characteristics of devices including the effects of their parasitic elements. Using these models, an optimizer can estimate the characteristic of a designed LNA precisely without electromagnetic simulations and gives us the design values of an LNA when the layout constraint is ignored. Starting from the values, a four-stage LNA with a GBCA stage is designed very easily even though the layout constraint is considered and fabricated by a 65nm LP CMOS process. The fabricated LNA is measured, and it is confirmed that it achieves 18.5GHz bandwidth and over 24.3dB gain with 50.6mW power consumption. This is the first LNA to achieve a gain bandwidth of over 300GHz in the E-band among the LNAs utilizing any kind of semiconductor technologies. In this paper, we have proved that CMOS technology, which is suitable for baseband and digital circuitry, is applicable to a communication system covering the entire E-band.

Device modeling techniques for high-frequency circuits operating at over 100 GHz are presented. We have proposed the bond-based design as an accurate high-frequency circuit design method. Because layout parasitic extractions (LPE) are not required in the bond-based design, it can be applied high-frequency circuit design at over 100 GHz. However, customized device models are indispensable for the bond-based design. In this paper, device modeling techniques for high-frequency circuit design using the bond-based design are proposed. The customized device model for MOSFETs, transmission lines and pads are introduced. By using customized device models, the difference between the simulated and measured gains of an amplifier is improved to less than 0.6 dB at 120 GHz.

An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.

In this paper, we propose a radio frequency (RF) anti-aliasing filter design method considering the effect of a roll-off characteristic on a noise figure (NF) in the direct RF undersampling receiver. The proposed method is useful for broadband reception that a system bandwidth (BW) has nearly half of the sampling frequency (1/2 fs). When the system BW is extended nearly 1/2 fs, the roll-off band is out of the desired Nyquist zone and it affects NF additionally. The proposed method offers a design target regarding the roll-off characteristic not only the rejection ratio. The target is helpful as a design guide to meet the allowed NF. We design the filter based on the proposed method and it is applied to the direct RF undersampling on-board receiver for Ka-band high throughput satellite (HTS). The measured NF value of the implemented receiver almost matched the designed value. Moreover, the receiver achieved the reception bandwidth which is 90% of 1/2 fs.

We propose a spectrum regeneration and demodulation method for multiple direct RF undersampled real signals by using a new algorithm. Many methods have been proposed to regenerate the RF spectrum by using undersampling because of its simple circuit architecture. However, it is difficult to regenerate the spectrum from a real signal that has a band wider than a half of the sampling frequency, because it is difficult to include complex conjugate relation of the folded spectrum into the linear algebraic equation in this case. We propose a new spectrum regeneration method from direct undersampled real signals that uses multiple clocks and an extended algorithm considering the complex conjugate relation. Simulations are used to verify the potential of this method. The validity of the proposed method is verified by using the simulation data and the measured data. We also apply this algorithm to the demodulation system.

In this paper, we proposed low power consumption ASK transmitter based on the direct modulated oscillator at 60GHz-band. To achieve the proposed transmitter, high power-efficient oscillator and loss less modulator are designed. Moreover combined on-chip resonator and antenna to remove the buffer amplifier of the transmitter to reduce the power consumption and size. The proposed transmitter has been fabricated in standard 65nm CMOS process. The core area is 1130µm×590µm with pads. The operation frequency is 60.4GHz. The BER of 10^-6 is achieved under 50Mbps with power consumption of less than 260µW including the buffer amplifier. Using the proposed combined on-chip resonator and antenna, which need no buffer amplifier for transmitter and the power consumption is reduced to 180µW.

To reduce the complexity of direct radio frequency (RF) undersampling real-time spectrum monitoring in wireless Internet of Things (IoT) bands (920MHz, 2.4GHz, and 5 GHz bands), a design method of sampling frequencies is proposed in this paper. The Direct RF Undersampling receiver architecture enables the use of ADC with sampling clock lower frequency than receiving RF signal, but it needs RF signal identification signal processing from folded spectrums with multiple sampling clock frequencies. The proposed design method allows fewer sampling frequencies to be used than the conventional design method for continuous frequency range (D.C. to 5GHz-band). The proposed method reduced 2 sampling frequencies in wireless IoT bands case compared with the continuous range. The design result using the proposed method is verified by measurement.

To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 µm 1P5M CMOS process. The core size is 10.8 µm10.5 µm. The power consumption of the ILO is 9.6 µW at 250 MHz, 255 µW at 2.4 GHz and 1.47 mW at 4.8 GHz. The phase noise is -105 dBc/Hz at a 1 MHz offset.

RF under sampling is more suitable for Satellite receiver systems in comparison to terrestrial systems. In conventional RF under sampling the minimum sampling frequency (fs) should be atleast twice the system bandwidth; therefore for a system with a wide bandwidth, a relatively high fs is necessary. In this paper we propose a direct RF under sampling reception method that halves fs. The proposed f's is achieved by folding in band noise in half. A method of adapting f's for the reception of signals in different channels is also proposed; this ensures that the SNR is not degraded for any channel. To evaluate the proposed technique's performance and compare it to the conventional case a 3 channel, 1 GHz band test receiver and it's key device (i.e. S/H circuit) are developed. Using SNR and EVM as performance indexes, the performance of the proposed technique has been evaluated and compared to that of the conventional technique. The evaluation results show that the proposed technique can achieve the same performance as conventional RF under sampling for all 3 channels, using only half of the sampling frequency of the conventional technique.

The design and measured results of a 120 GHz/140 GHz dual-channel OOK (ON-OFF Keying) receiver are presented in this paper. Because a signal with very wide frequency width is difficult to process in a single-channel receiver, a dual-channel configuration with channel selection is adopted in the proposed receiver. The proposed receiver is fabricated using 65 nm CMOS technology. The measured data rate of 3.0 and 3.6 Gbps, minimum sensitivity of -25.6 and -27.1 dBm, communication distance of 0.30 and 0.38 m are achieved in the 120- and 140-GHz receiver, respectively. The correct channel selection is achieved in the 120-GHz receiver. These results indicate the possibility of the CMOS multiband receiver operating at over 100 GHz for low-power high-speed proximity wireless communication systems.

Accurate device models are very important for the design of high-frequency circuits. One of the factors degrading the accuracy of device models appears during the de-embedding procedure. Generally, to obtain device characteristics without parasitic elements such as pads, a de-embedding procedure is essential. However, some errors are introduced during this procedure, which degrades the accuracy of device models. In this paper, we demonstrate that such errors due to de-embedding are cancelled in cascade circuit design, meaning that cascade circuits can be designed without knowing the actual characteristics of devices. Because it is difficult to know the actual characteristics of devices at a high frequency, the cancellation of the de-embedding error is expected to improve the accuracy of device models at high frequencies. After giving a theoretical treatment of de-embedding error cancellation, we report the results of simulations and measurements performed for verification.

In this paper, we propose a direct digital RF transmitter with a 1-bit band-pass delta-sigma modulator (BP-DSM) that uses high order image components of the 7th Nyquist zone in Manchester coding for microwave and milimeter wave application. Compared to the conventional non-return-to-zero (NRZ) coding, in which the high order image components of 1-bit BP-DSM attenuate severely in the form of sinc function, the proposed 1-bit direct digital RF transmitter in Manchester code can improve the output power and signal-to-noise ratio (SNR) of the image components at specific (4n-1)th and (4n-2)th Nyquist Zone, which is confirmed by calculating of the power spectral density. Measurements are made to compare three types of 1-bit digital-to-analog converter (DAC) signal in output power and SNR; NRZ, 50% duty return-to-zero (RZ) and Manchester coding. By using 1 Vpp/8Gbps DAC output, 1-bit signals in Manchester coding show the highest output power of -20.3dBm and SNR of 40.3dB at 7th Nyquist Zone (26GHz) in CW condition. As a result, compared to NRZ and RZ coding, at 7th Nyquist zone, the output power is improved by 8.1dB and 6dB, respectively. Meanwhile, the SNR is improved by 7.6dB and 4.9dB, respectively. In 5Mbps-QPSK condition, 1-bit signals in Manchester code show the lowest error vector magnitude (EVM) of 2.4% and the highest adjacent channel leakage ratio (ACLR) of 38.2dB with the highest output power of -18.5dBm at 7th Nyquist Zone (26GHz), respectively, compared to the NRZ and 50% duty RZ coding. The measurement and simulation results of the image component of 1-bit signals at 7th Nyquist Zone (26GHz) are consistent with the calculation results.

On-chip transmission lines are widely used in ultrahigh-frequency integrated circuits. One of the issues in modeling such transmission lines is that no reference impedance can be established on a chip. Conventionally, the parallel admittance Yp has been adopted as a reference parameter for on-chip transmission lines instead of a reference characteristic impedance of 50Ω. In the case of CMOS processes, however, Yp can have complicated characteristics in the short-millimeter-wave band owing to the frequency characteristics of the electric permittivity of low-k materials, which cannot be expressed using a simple circuit. To solve this problem, we propose the use of the series impedance Zs as a reference parameter for transmission-line modeling since it basically can be determined from the geometrical dimensions and the frequency-stable permeability and resistivity. The parameters of transmission lines obtained by the proposed method were compared with those obtained by conventional methods using a 40nm CMOS process. By using the equivalent circuit model of Yp along with RLC resonators, it is shown that the peaks of the frequency characteristics of Yp can be used to explain the absorption spectrum of the dielectric. This suggests that the proposed method is suitable for CMOS short-millimeter-wave transmission lines.