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[Author] Shugang WEI(5hit)

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  • Compact Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits

    Shugang WEI  Kensuke SHIMIZU  

     
    PAPER-Non-Binary Architectures

      Vol:
    E82-C No:9
      Page(s):
    1647-1654

    A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

  • Synthesis of Multilevel Feed-Forward NAND Networks

    Kensuke SHIMIZU  Shugang WEI  

     
    LETTER-Computer System

      Vol:
    E69-E No:7
      Page(s):
    785-787

    A method for the synthesis of near optimal NAND networks is presented. At first, a given logical function is realized as a multilevel network with a minimum number of negative gates. Next this is transformed into a NAND network. Since procedures presented here do not require backtracking, they are quite efficient.

  • A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation

    Shugang WEI  Kensuke SHIMIZU  

     
    PAPER-Theory/Models of Computation

      Vol:
    E83-D No:12
      Page(s):
    2056-2064

    A novel residue arithmetic algorithm using radix-2 signed-digit (SD) number representation is presented. By this representation, memoryless residue arithmetic circuits using SD adders can be implemented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a p-digit radix-2 SD number system is introduced to simplify the residue operation. For a modulus m, 2p-1 m 2p+2p-1-1, in a residue number system (RNS), the modulo m addition is performed by using two p-digit SD adders, one for the addition and one for the residue operation. Thus, the modulo m addition time is independent of the word length of operands. When m=2p or m= 2p 1, the modulo m addition is implemented by using only one SD adder. Moreover, a modulo m multiplier is constructed using a binary modulo m SD adder tree, and the modulo m multiplication can be performed in a time proportional to log 2 p. The VHDL implementation method for the presented algorithm is also discussed. The design and simulation results of some residue arithmetic circuits show that high speed residue arithmetic circuits can be obtained by the presented algorithms.

  • Modulo 2p-1 Arithmetic Hardware Algorithm Using Signed-Digit Number Representation

    Shugang WEI  Kensuke SHIMIZU  

     
    LETTER-Computer Hardware and Design

      Vol:
    E79-D No:3
      Page(s):
    242-246

    To realize high-speed computations in a residue number system (RNS), an implementation method for residue arithmetic circuits using signed-digit (SD) number representation is proposed. Integers mp = (2p-1) known as Mersenne numbers are used as moduli, so that modulo mp addition can be performed by an end-around-carry SD adder and the addition time is independent of the word length of operands. Using a binary modulo mp SD adder tree, the modulo mp multiplication can be performed in a time proportional to log2p.

  • Dynamic Range Compression Characteristics Using an Interpolating Polynomial for Digital Audio Systems

    Shugang WEI  Kensuke SHIMIZU  

     
    LETTER-Digital Signal Processing

      Vol:
    E88-A No:2
      Page(s):
    586-589

    An audio signal level compressor is presented, which is based on the approximation algorithm using an interpolating polynomial. To implement a compression characteristic in a digital audio system, a power calculation with fractional numbers is required and it is difficult to be performed directly in digital circuits. We introduce a polynomial expression to approximate the power operation, then the gain calculation is easily performed with a number of additions, multiplications and a division. Newton's interpolation formula is used to calculate the compression characteristics in a very short time and the obtained compression characteristics are very close to the ideal ones.