Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant gm, etc. ), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc. ) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.

This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0), -1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant-binary addition/subtraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42. 1 ns with 0.35 µm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730µm 910 µm area.

In this paper, we propose a method, called PORT-D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is estimated by the revised BDD traversal method. The revised BDD traversal method calculates switching activity of gate output by constructing OBDD's without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experimental results for benchmark circuits show PORT-D reduces the average power dissipation more than the number of transistors. Furthermore, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization capability than PORT-D.

A new electromagnetic coupling structure has been proposed for a millimeter wave DR-VCO. The structure consists of a microstrip substrate placed on a planar type dielectric resonator and provides a strongly confined electromagnetic field and a high Q. The resonator used in this structure is a TE010 mode dielectric resonator composed of a dielectric substrate and electrodes on both sides of the substrate. Each electrode has a circular hollow patch. A microstrip circuit substrate with an aperture on the ground electrode is stacked on the resonator. The resonator is magnetically coupled to the transmission line through the aperture. The coupling structure has advantages as follows: (a) The electromagnetic field is strongly confined at the hollow patch, and (b) unloaded Q reduction is only 18% under a strong coupling. When the structure is used as a resonant circuit for a DR-VCO, the circuit can be small because the transmission lines to be isolated from the resonator are able to be placed near the resonator. Both a large loaded Q and a large reflection coefficient of a resonant circuit are obtained with the structure. Fabricated DR-VCO has following performances. The oscillation center frequency is 30. 242 GHz and the frequency tuning range is 91 MHz when the control voltage varies 2 to 10 V. An output power of more than 7.3 dBm and a C/N of 90 dBc/Hz at 100 kHz offset are obtained at the frequency range.

Simple disjunctive decomposition is a special case of logic function decompositions, where variables are divided into two disjoint sets and there is only one newly introduced variable. It offers an optimal structure for a single-output function. This paper presents two techniques that enable us to apply simple disjunctive decompositions with little overhead. Firstly, we propose a method to find symple disjunctive decomposition forms efficiently by limiting decomposition types to be found to two: a decomposition where the bound set is a set of symmetric variables and a decomposition where the output function is a 2-input function. Secondly, we propose an algorithm that constructs a new logic representation for a simple disjunctive decomposition just by assigning constant values to variables in the original representation. The algorithm enables us to apply the decomposition with keeping good structures of the original representation. We performed experiments for decomposing functions and confirmed the efficiency of our method. We also performed experiments for restructuring fanout free cones of multi-level logic circuits, and obtained better results than when not restructuring them.

In this paper we present two traffic control approaches, a circuit emulation traffic control (CETC) and an adaptive priority traffic control (APTC) for supporting voice services in ATM networks. Most voice services can be handled as CBR traffic, this causes a lot of wasted bandwidth. Sending voice through VBR (variable bit rate) may be a better alternative, because it allows the network to allocate voice bandwidth on demand. In CETC, the service discipline guarantees the quality of service (QOS) for voice circuits. Through mathematical analysis, we show that CETC features an adequate performance in delay-jitter. Moreover, it is feasible in implementation. We also present an APTC approach which uses a dynamic buffer allocation scheme to adjust the buffer size based on the real traffic need, as well as employs an adaptive priority queuing technique to handle various delay requirements for VBR voice traffic. It provides an adequate QOS for voice circuits in addition to improving the multiplexing gain. Simulation results show that voice traffic get satisfied delay performance using our approaches. It may fulfill the emerging needs of voice service over ATM networks.

A new broadband buffer circuit technique and its analytical design method are proposed for a high-speed decision circuit featuring both a higher input sensitivity and a larger phase margin. The buffer circuit characteristics are significantly improved by employing a series peaking source follower (SPSF), where a peaking inductor is inserted between the first and second source follower stages. Optimization of the peaking inductance successfully enhances the 3-dB bandwidth of the data-input buffer and the clock buffer by 7 GHz for both, over conventional double-stage source follower SCFL buffers. The proposed circuit technique and design method are applied to a 10-Gbit/s decision circuit by the use of production-level 0. 5 µm GaAs MESFETs. The fabricated decision circuit achieves a data input sensitivity of 43 mVp-p and a phase margin of 240 both at 10-Gbit/s: a 230 mVp-p smaller input sensitivity and a 35 larger phase margin than those of conventional non-peaking inductor types.

We have studied an in situ edge preparation process and the effect of a substrate rotation during the edge preparation in order to improve the uniformity and electrical characteristics of high-Tc edge-type Josephson junctions. The improved YBa2Cu3Ox/PrBa2Cu3Ox/YBa2Cu3Ox edge junctions showed small 1σ-critical current spreads as low as 10% for 12 junctions. We have confirmed that the spreads do not increase significantly by adding groundplane over the junctions. In this paper, we will describe these processes developed for the fabrication of high-Tc superconducting integrated circuits.

In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.

We have designed rapid single-flux-quantum (RSFQ) adder circuits using two different architectures: one is the conventional architecture employing globally synchronous clocking and the other is the data-driven self-timed (DDST) architecture. It has been pointed out that the timing margin of the RSFQ logic is very sensitive to the circuit parameter variations which are induced by the fabrication process and the device parameter uncertainty. Considering the physical timing in the circuits, we have shown that the DDST architecture is advantageous for realizing RSFQ circuits operating at very high frequencies. We have also calculated the theoretical circuit yield of the DDST adders and shown that a four-bit system operating at 10 GHz is feasible with sufficient operating margin, considering the present 1 kA/cm2 Nb Josephson technology.

We present two types of ICF (INHIBIT Controlled by Fluxon) gates as the basic circuits of the phase-mode logic family, and fabricate an adder circuit. The experimental result demonstrates that the carry operation followed up to 99 GHz input pulses. The performance of Josephson devices is improved by the use of junctions with high current density (Jc). We may use the high-Jc junctions without external resistive shunt in the phase-mode logic circuits because of reduction of the junction hysteresis. One of the ways to overcome the large area occupancy for geometric inductance is to utilize the effective inductance of a Josephson junction itself. We investigate a circuit construction with high-Jc inductor junctions, intrinsically overdumped junctions and junction-type resistors for the compactness of circuit integration, and discuss various aspects of the circuit construction.

Planar lightwave circuits (PLCs) provide various important devices for optical wavelength division multiplexing (WDM) systems, subscriber networks and etc. This paper reviews the recent progress and future prospects of PLC technologies including arrayed-waveguide grating multiplexers, optical add/drop multiplexers, programmable dispersion equalizers and hybrid optoelectronics integration technologies.

High- and low-reflection Bragg gratings with a flat-top spectral response free from ripples are proposed. Add/drop filters are created based on gratings photoinduced on planar waveguides by using the new design schemes. The measured spectral responses for the high and low reflection gratings are in good agreement with the calculated ones, and show the flat-top spectral responses.

This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.

The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable due to the existence of random pattern resistant faults. In this paper, we present a method for improving the random pattern testability of logic circuits by partial circuit duplication approach. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.

We have specified typical fabrication defects of the current injection logic gates with four Josephson junctions (4JL gates), and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that current testing may possibly achieve a high defect coverage while logic testing cannot detect almost half defects.

Cellular automata (CA) implementations are expected as potential test-pattern generators (TPGs) for Built-In Self-Testing of VLSI circuits, in which highly random parallel patterns ought to be generated with simple hardware. Objective here is to design one-dimensional, binary, and linear CA implementations with cyclic boundary conditions that can operate on maximum length of period. To provide maximum period of operations, it is necessary to bring some irregularities into the configurations. It is also expected for TPGs to make maximum or sufficiently long period of operations to prevent re-initialization. Our approach is to generate transition matrices based on fast parallel implementations of LFSRs which have trinomials as characteristic polynomials and then to modify the diagonal components. Some notable properties of diagonal vectors were observed.

Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the desired clock speed is identified, it is necessary to locate the delay fault(s) affecting the circuit in order to remedy the situation. In this paper, we present a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. We first present the basic rules for deducing suspected faults based on the multiple gate delay fault assumption. Next, in order to improve diagnostic resolution, we introduce rules for deducing non-existent faults based on the fault-free responses at the primary outputs. Using these rules, we present the detailed method for diagnosing multiple delay faults based on paths sensitized by test-pairs generated for marginal delays and gate delay faults [7]. Finally, we present results obtained from experiments on the ISCAS '85 benchmark circuits. The experimental results show the effectiveness of our method.