This paper describes numerical analyses of resistive mixer operation, followed by measured performances of a V-band (50 - 75 GHz) monolithic InP HEMT resistive mixer operable with a very low LO power. Our model assumes that the channel conductance of the InP HEMT can be described by three linear functions according to the applied gate voltage. The calculated results obtained with the model have shown that the LO power level required for mixer operation is determined by the gate bias voltage and that a device with abrupt conductance shifts is suited to low LO power operation for a resistive mixer. It is also shown that conversion loss saturation of a resistive mixer is caused by its channel conductance saturation. A V-band monolithic resistive mixer has been designed and fabricated using Coplanar Waveguides (CPW) and a 0.15 mm InP HEMT with abrupt channel shifts. Good agreement between measured and simulated conversion losses are obtained. A minimum conversion loss of 8.4 dB is achieved at the 55 GHz RF-frequency and the -2 dBm LO power. It also exhibits an excellent IF output linearity to allow the 1 dB compression RF input level to be comparable with LO power, indicating good intermodulation performance. It is demonstrated that the proposed simple model of the channel conductance can easily calculate conversion characteristics of a resistive mixer with high accuracy.

A new broadband buffer circuit technique and its analytical design method are proposed for a high-speed decision circuit featuring both a higher input sensitivity and a larger phase margin. The buffer circuit characteristics are significantly improved by employing a series peaking source follower (SPSF), where a peaking inductor is inserted between the first and second source follower stages. Optimization of the peaking inductance successfully enhances the 3-dB bandwidth of the data-input buffer and the clock buffer by 7 GHz for both, over conventional double-stage source follower SCFL buffers. The proposed circuit technique and design method are applied to a 10-Gbit/s decision circuit by the use of production-level 0. 5 µm GaAs MESFETs. The fabricated decision circuit achieves a data input sensitivity of 43 mVp-p and a phase margin of 240 both at 10-Gbit/s: a 230 mVp-p smaller input sensitivity and a 35 larger phase margin than those of conventional non-peaking inductor types.

This paper describes the behavior of voids that were formed due to electromigration and diffusion in the interconnections of gold during a DC bias tests of GaAs ICs to current densities in the interconnections of 0.67 106 A/cm2 to 1.27 106 A/cm2 in the high temperature range of 230 to 260. We have found that the voids were formed at the centers in the cross sections of the interconnections and that gold is left around the voids, which means current still flows after the void formation. We have carefully observed the movement of the anode and cathode side edge of the voids during the tests and found that edges moved toward the cathode, in the direction opposite to the electron flow. This direction is constant. Also, the voids are extended, which means that the velocity of the cathode side edge is greater than that of the anode side edge. The velocity of the edges almost proportionally increased with the current density. The constant edge movement direction and the velocity of the edge dependence on the current density suggest that one of the causes of the edge movement is electromigration. The velocity of the edge depends on the distance between the anode side edge of the void and the through hole. The velocity increases in accordance with a decrease in the distance. This means that one of the causes of the edge movement is the diffusion of gold atoms by a concentration and pressure gradient. The GaAs IC failed at almost the same time as the voids appeared. It is important for reliability to prevent the formation of voids caused by electromigration and diffusion.