A new harmonic termination that controls the waveform of the drain current to be rectangular is developed for high-efficiency power amplifier modules. Its harmonic termination is a short circuit at the third harmonic and a non-short circuit at the second harmonic. It is found experimentally and confirmed by simulation that the load-matching condition at the third-order harmonic improves the efficiency of a transistor by more than 13%. By using this tuning, 57.7% power-added efficiency of the module is achieved at the output power of 29.9 dBm with ACP of -50 dBc, NACP of -65 dBc at 925 MHz and Vdd of 3.5 V.

This paper describes the behavior of voids that were formed due to electromigration and diffusion in the interconnections of gold during a DC bias tests of GaAs ICs to current densities in the interconnections of 0.67 106 A/cm2 to 1.27 106 A/cm2 in the high temperature range of 230 to 260. We have found that the voids were formed at the centers in the cross sections of the interconnections and that gold is left around the voids, which means current still flows after the void formation. We have carefully observed the movement of the anode and cathode side edge of the voids during the tests and found that edges moved toward the cathode, in the direction opposite to the electron flow. This direction is constant. Also, the voids are extended, which means that the velocity of the cathode side edge is greater than that of the anode side edge. The velocity of the edges almost proportionally increased with the current density. The constant edge movement direction and the velocity of the edge dependence on the current density suggest that one of the causes of the edge movement is electromigration. The velocity of the edge depends on the distance between the anode side edge of the void and the through hole. The velocity increases in accordance with a decrease in the distance. This means that one of the causes of the edge movement is the diffusion of gold atoms by a concentration and pressure gradient. The GaAs IC failed at almost the same time as the voids appeared. It is important for reliability to prevent the formation of voids caused by electromigration and diffusion.

An L-Band high efficiency and low distortion multi-stage amplifier using self phase distortion compensation technique is presented. In this amplifier, the bias condition of the driver-stage transistor is tuned to compensate the phase distortion of the power-stage transistor, and the load and source impedances of the driver-stage and power-stage transistors are optimized to achieve the maximum efficiency with a specified adjacent channel leakage power (ACP) for multi-stage amplifier. The developed amplifier achieves a power added efficiency (Eadd) of 42.8% and an output power (Pout) of 26.8 dBm with an ACP of -38 dBc at 1.95 GHz for wide-band code-division multiple-access (W-CDMA) cellular phones.

GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer chip sets have been successfully developed. The 64-bit 156 Mb/s parallel data output or input of these chip sets can be directly connected to CMOS LSIs. These chip sets consist of a 10Gb/s 4: 1 MUX IC, a 10 Gb/s 1: 4 DEMUX IC, four 2.5 Gb/s 16: 1 MUX LSIs and four 2.5 Gb/s 1: 16 DEMUX LSIs. This multi-chip construction is adopted for low power dissipation and high yield. The basic circuit employed in the 10 Gb/s4: 1 MUX/DEMUX ICs is an SCFL circuit using 0.4 µm-gate FETs with a power supply of -5.2 V, and that in 2.5 Gb/s 16: 1 MUX/DEMUX LSIs is a DCFL circuit using 0.6 µm-gate FETs with a power supply of -2.0 V. These chip sets have functions for synchronization among these ICs and to enable bit shift to make the system design easier. In the 10 Gb/s 4: 1 MUX IC, a timing adjuster is adopted. This timing adjuster can delay the timing of the most critical path by 50 ps. Even if the delay times are out of order due to fluctuations in process, temperature, power supply voltage and other factors, this timing can be revised and the 4: 1 MUX IC can operate at 10 Gb/s. Furthermore, a 48-pin quad flat package for 10 Gb/s 4: 1 MUX/DEMUX ICs has been newly developed. The measured insertion loss is 1.7 dB (at 10 GHz), and the isolation is less than -20 dB (at 10 GHz). These values are sufficient in practical usage. Measurements of these chip sets show desirable performance at the target 10 Gb/s. The power dissipations of the 64: 1 MUX/DEMUX chip sets are 10.3 W and 8.2 W, respectively. These chip sets is expected to contribute to high speed telecommunication systems.

A constant voltage/constant current (CV/CC) parallel operation heterojunction bipolar transistor (HBT) power amplifier (PA) configuration is presented, and its design method is described. A resistor base feed (CC mode) HBT is connected to an inductor base feed (CV mode) HBT in parallel, and compensates the gain expansion of the CV mode HBT due to near class-B operation. By adding CC mode HBT, the total quiescent current can be decreased from 32 mA to 23 mA with adjacent channel leakage power ratio (ACPR) < -40.0 dBc. At the maximum output power region, the fabricated PA achieves output power (Pout) of 26.8 dBm and power added efficiency (PAE) of 42.0% with ACPR of -40.0 dBc, and shows the comparable performances with a conventional PA using CV mode HBT.

In order to establish design and measurement technologies for an LSI that features high speed operation and low power dissipation, GaAs 2.5 Gbps 16 bit MUX/DEMUX LSIs have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. For the purpose of achieving stable operation against the transistor parameter deviation, a timing design called clock tracking is employed. Moreover, to ensure accurate performance measurement, a new measurement system is introduced. The measurement system consists of an error rate detector (ERD), a pulse pattern generator (PPG) and a high speed tester (HST). The performances tested by the measurement system show the power consumptions of MUX and DEMUX LSIs are 1.35 W and 0.95 W. Input phase margin of DEMUX LSI is 290 degrees at 2.5 Gbps operation. The technologies obtained through development of these MUX/DEMUX LSIs are applicable to other high speed and low power LSIs.