This paper describes numerical analyses of resistive mixer operation, followed by measured performances of a V-band (50 - 75 GHz) monolithic InP HEMT resistive mixer operable with a very low LO power. Our model assumes that the channel conductance of the InP HEMT can be described by three linear functions according to the applied gate voltage. The calculated results obtained with the model have shown that the LO power level required for mixer operation is determined by the gate bias voltage and that a device with abrupt conductance shifts is suited to low LO power operation for a resistive mixer. It is also shown that conversion loss saturation of a resistive mixer is caused by its channel conductance saturation. A V-band monolithic resistive mixer has been designed and fabricated using Coplanar Waveguides (CPW) and a 0.15 mm InP HEMT with abrupt channel shifts. Good agreement between measured and simulated conversion losses are obtained. A minimum conversion loss of 8.4 dB is achieved at the 55 GHz RF-frequency and the -2 dBm LO power. It also exhibits an excellent IF output linearity to allow the 1 dB compression RF input level to be comparable with LO power, indicating good intermodulation performance. It is demonstrated that the proposed simple model of the channel conductance can easily calculate conversion characteristics of a resistive mixer with high accuracy.

This paper describes two different types of GaAs-HBT compatible, base-collector diode 0/20-dB step attenuators--diode-linearizer type and harmonics-trap type--for 3.5-GHz-band wireless applications. The two attenuators use an AC-coupled, stacked type diode switch topology featuring high power handling capability with low bias current operation. Compared to a conventional diode switch topology, this topology can improve the capability of more than 6 dB with the same bias current. In addition, successful incorporation of a shunt diode linearizer and second- and third-harmonic traps into the attenuators gives the IM3 distortion improvement of more than 7 dB in the high power ranging from 16 dBm to 18 dBm even in the 20-dB attenuation mode when IM3 distortion levels are basically easy to degrade. Measurement results show that both the attenuators are capable of delivering power handling capability (P0.2 dB) of more than 18 dBm with IM3 levels of less than -35 dBc at an 18-dBm input power while drawing low bias currents of 3.8 mA and 6.8 mA in the thru and attenuation modes from 0/5-V complementary supplies. Measured insertion losses of the linearizer-type and harmonics-trap type attenuators in the thru mode are as low as 1.4 dB and 2.5 dB, respectively.

This paper describes a narrow pass-band optical filter utilizing a wavelength-sensitive power-transfer characteristic in the directional coupler composed of the K-and Ag-ion exchange waveguides which have greatly different dispersion relations caused by the large mismatch in the index profile of the waveguide cross-section. A narrow pass-band width of about 7 nm is measured in the filter fabricated in the soda-lime glass substrate. The fabrication technique with two-step ion-exchange of the K-and Ag-ions, is also presented together with a quick design method.

This paper describes a sub 1-V low noise amplifier (LNA) fabricated using a 0.35 µm SOI (silicon on insulator) CMOS process. The SOI devices have high speed performance even at low operating voltage (below 1 V) because of their smaller parasitic capacitance at source and drain than those of bulk MOSs. A body of a MOSFET can be controlled by using a field shield (FS) plate. The transistor body of the LNA is connected to its gate. The threshold voltage of the transistor becomes lower due to the body-biased effect so that a large drain current keeps the gain high, and active-body control improves the 1-dB gain compression point. A gain of 7.0 dB and a Noise Figure (NF) of 3.6 dB are obtained at 1.0 V and 1.9 GHz. The output power at the 1-dB gain compression point is +1.5 dBm. The gain and the output power at the 1-dB gain compression point are higher by 1.2 dB and 2.9 dB respectively than those of a conventionally body-fixed LNA. A 5.5 dB gain is also obtained at the supply voltage of 0.5 V.

This paper describes the circuit design and measurement results of a new GaAs-HBT RF power detector proposed for use in WiMAX and wireless LAN transmitter applications. The detector, which is based on a simple current-mirror topology, occupies a small die area. It is, therefore, not only easy to implement together with a GaAs-HBT power amplifier, but can also offer approximately logarithmic (linear-in-dB) characteristics. Because it can also be driven with small voltage amplitudes, it is suitable for base-terminal monitoring at an HBT power stage. When the detector is used as a base-terminal power monitor, an appropriate base resistance added to the detection HBT effectively suppresses frequency dispersion of the detected voltage characteristics. Measurements of a prototype detector incorporated into a single-stage HBT power amplifier fabricated on the same die are as follows. The detector is capable of delivering a detected voltage of 0.35-2.5 V with a slope of less than 0.17 V/dB over a 4-to-24-dBm output power range at 3.5 GHz while drawing a current of less than 1.8 mA from a 2.85-V supply. While satisfying a log conformance error of less than 1 dB over an amplifier output power range from 4 dBm to 24 dBm, it can also suppress the detected power dispersion within 0.18 dB at approximately 15 dBm of output power over a 3.1-3.9-GHz-wide frequency range. This dispersion value is approximately one-tenth that of a conventional collector-terminal-monitor-type diode detector.

This paper describes 2.4-GHz-band front-end building circuits--a down conversion mixer (DCM), a dual-modulus divide-by-4/5 prescaler, a transmit/receive antenna switch (SW), a power amplifier (PA), and a low noise amplifier (LNA). They are fabricated using a standard bulk 0.18 µm CMOS process with a lower current consumption than bipolar circuits, and can operate at the low supply voltage of 1.8 V. Meshed-shielded pads are adopted for lower receiver circuit noise. Pads shielded by metals become cracked when they are bounded, therefore silicided active areas are used as shields instead of metals to avoid these cracks. The meshed shields achieve lower parasitic pad capacitors without parasitic resistors, and also act as dummy active areas. The proposed DCM has a high IP3 characteristic. The DCM has a cascode FET configuration and LO power is injected into the lower FET. By keeping the drain-source voltage of the upper transistor large, the nonlinearity of the drain-source transconductance is reduced and a low distortion DCM is realized. It achieves a higher input referred IP3 with a higher conversion gain for almost the same current consumption of a conventional single-balanced mixer. The output referred IP3 is higher 5.0 dB than the single-balanced mixer. The proposed dual-modulus prescaler employs a fully-differential technique to achieve stable operation. In order to avoid errors, the fully-differential circuit gives the logic voltage swing margins. In addition, the differential technique also reduces the noise effect from the supply voltage line because of the common-mode signal rejection. The maximum operating frequency is 3.0 GHz, and the one flip-flop power consumption normalized by the maximum operating frequency is 180 µW/GHz.

This paper describes a 3.5 V operation InGaP HBT MMIC power amplifier module for use in GSM/EDGE dual-mode, 900/1800/1900 MHz triple band handset applications. Conventional GSM amplifiers have a high linear gain of 40 dB or more to realize efficiency operation in large gain compression state exceeding at least 5 dB. On the other hand, an EDGE amplifier needs a linear operation to prevent signal distortion. This means that a high linear gain amplifier cannot be applied to the EDGE amplifier, because the high gain leads to the high noise power in the receive band (Rx-noise). In order to solve this problem, we have changed the linear gain of the amplifier between GSM and EDGE mode. In EDGE mode, the stage number of the amplifier changes from three to two. To reduce a high gain, the first stage transistors in the amplifier is bypassed through the diode switches. This newly proposed bypass circuit enables a high gain in GSM mode and a low gain in EDGE, thus allowing the amplifier to operate with high efficiency in both modes while satisfying the Rx-noise specification. In conclusion, with diode switches and a band select switch built on the MMIC, the module delivers a Pout of 35.5 dBm and a PAE of about 50% for GSM900, a 33.4 dBm Pout and a 45% PAE for GSM1800/1900. While satisfying an error vector magnitude (EVM) of less than 4% and a receive-band noise power of less than -85 dBm/100 kHz, the module also delivers a 29.5 dBm Pout and a PAE of over 25% for EDGE900, a 28.5 dBm Pout and a PAE of over 25% for EDGE1800/1900.

This paper describes circuit design and measurement results of a newly proposed GaAs-HBT step-gain amplifier configuration and its application to a 3.3-3.6 GHz WiMAX power amplifier module for use in customer premises equipment. The step-gain amplifier implemented using only a usual HBT process is based on a current-mirror-based, base-collector diode switches and a passive attenuator core for the purpose of bypassing a power-gain stage. The stage allows an individual design approach in terms of gain and attenuation levels as well as large operating current reduction in the attenuation state. To confirm the effectiveness of the proposed step-gain amplifier, a prototype of the amplifier was designed and fabricated, and then a WiMAX power amplifier module was also designed and fabricated as an application example of the proposed configuration to an amplifier product. Measurements are as follows. For a 3.5-V power supply and a 3.5-GHz non-modulated signal, the step-gain amplifier delivers 23.7 dBm of 1-dB gain compressed output power and 10.7 dB of linear gain in the amplification state. In the attenuation state, the amplifier exhibits 21 dBm of 1-dB gain expanded input power, -9.7 dB of gain, and 15 mA of current dissipation while keeping the gain stage switched off and maintaining input and output return loss of less than -10 dB at a 3.5-GHz band. The WiMAX amplifier operating with a 5-V supply voltage and a 64-QAM modulated signal is capable of delivering a 28.5-dBm linear output power, a 37-39 dB gain, and 15% of PAE over a wide frequency range from 3.3 to 3.6 GHz in the high-gain state while keeping error vector magnitude as low as 2.5%. This amplifier, which incorporates the proposed step-gain configuration into its interstage, enables a 24-dB gain reduction and a 45-mA large quiescent current reduction in the low-gain state.

A new GaAs negative voltage generator suitable for biasing a GaAs MESFET power amplifier has been successfully developed and applied to a 1.9-GHz single-chip transmit/receive (T/R)-MMIC front-end including a power amplifier, a T/R-switch, and so on. To meet various requirements necessary for integration with a power amplifier, four new circuit techniques are introduced into this generator: (1)complementary charge pump operation to suppress spurious outputs. (2)an SCFL-to-DCFL cross-coupled level shifter to ensure a wide operation voltage range, (3)a level control circuit to reduce output voltage deviation caused by output current, and (4)interface and layout designs to achieve sufficient isolation between the power amplifier and the generator. The generator was incorporated into the MMIC front-end, and it was tested with a 30-lead shrink small outline package. With 20-to-500-MHz external input signals of more than -15 dBm, the generator produces negative voltages from -1.0 to -2.6 V for a wide range of suppiy voltages from 1.6 to 4.5 V. The current consumption is as low as 3.2 mA at 3 V. When a 22-dBm output is delivered through the power amplifier biased by the generator, low spurious outputs below -70 dBc are achieved. and gate-bias voltage deviations are suppressed to within 0.06 V even when a gate current of -140 µA flows through the amplifier. The generator also enables high speed operation of charge time below 200 ns, which is effective in TDMA systems such as digital cordless telephone systems. In layout design, electromagnetic simulation was utilized for estimating sufficient isolation between circuits in the MMIC. This negative voltage generator and its application techniques will enable GaAs high-density integration devices as well as single voltage operation of a GaAs MESFET power amplifier.

A single-chip GaAs Transmit/Receive (T/R)-MMIC front-end has been developed which is applicable to 1. 9-GHz personal communication terminals such as digital cordless phones. This chip is fabricated using a planar self-aligned gate FET useful for low-cost and high-volume production. The chip integrates RF front-end analog circuits a power amplifier, a T/R-switch, and a low-noise amplifier. Additionally integrated are a newly developed voltage-doubler negative-voltage generator (VDNVG) and a control logic circuit to control transmit and receive functions, enabling both a single-voltage operation and an enhanced power handling capability of the switch, even under a single low-voltage supply condition of 2 V. The power amplifier incorporated onto the chip is capable of delivering a 21 dBm output power at a 39% efficiency, and a 30 dB associated gain with a 2 V single power supply in the transmit mode. The gain and efficiency are higher than those of the previously reported amplifier operating with a 2 V single power supply. The VDNVG produces a step-up voltage of 2. 9 V as well as a negative voltage of -1. 8 V from a 2 V power supply, operating with a charge time of less than 0. 25 µs. The control logic circuit on the chip has a newly designed interface circuit utilizing the step-up voltage and negative voltage, thereby enabling the chip to handle high power outputs over 24 dBm with a low operating voltage of 2 V. In the receive mode, a 1. 7 dB noise figure and a 0. 6 dB insertion loss are achieved with a current dissipation of 3. 6 mA. The developed MMIC, which is the first reported 2 V single-voltage operation T/R-MMIC front-end, is expected to contribute to the size and weight reductions in personal communication terminals.

This paper describes, for the first time, an experimental study on the layout design considerations of GaAs HBT MMIC switchable-amplifier-chain-based power amplifiers (SWPAs) for CDMA handsets. The transient response of the quiescent current and output power (Pout) in GaAs HBT power amplifiers that consist of a main chain and a sub-chain is often affected by a thermal coupling between power stages and their bias circuits in the same chain or a thermal coupling between power stages and/or their bias circuits in different chains. In particular, excessively strong thermal coupling inside the MMIC SWPA causes failure in 3GPP-compliant inner loop power control tests. An experimental study reveals that both the preheating in the main/sub-chains and appropriate thermal coupling inside the main chain are very effective in reducing the turn-on delay for the two-parallel-amplifier-chain topology; for example, i) the sub-power stage is arranged near the main power stage, ii) the sub-driver stage is placed near the main driver stage and iii) the main driver bias circuit is placed near the main power stage and the sub-power stage. The SWPA operating in Band 9 (1749.9 to 1784.9 MHz), which was designed and fabricated from the foregoing considerations, shows a remarkable improvement in the Pout turn-on delay: a reduced power level error of 0.74 dB from turn-off to turn-on in the sub-amplifier chain and a reduced power level error of over 0.30 dB from turn-off to turn-on in the main amplifier chain. The main RF power measurements conducted with a 3.4-V supply voltage and a Band 9 WCDMA HSDPA modulated signal are as follows. The SWPA delivers a Pout of 28.5 dBm, a power gain (Gp) of 28 dB, and a PAE of 39% while restricting the ACLR1 to less than -40 dBc in the main amplifier chain. In the sub-amplifier chain, 17 dBm of Pout, 23.5 dB of Gp, and 27% of PAE are obtained at the same ACLR1 level.

A new broadband buffer circuit technique and its analytical design method are proposed for a high-speed decision circuit featuring both a higher input sensitivity and a larger phase margin. The buffer circuit characteristics are significantly improved by employing a series peaking source follower (SPSF), where a peaking inductor is inserted between the first and second source follower stages. Optimization of the peaking inductance successfully enhances the 3-dB bandwidth of the data-input buffer and the clock buffer by 7 GHz for both, over conventional double-stage source follower SCFL buffers. The proposed circuit technique and design method are applied to a 10-Gbit/s decision circuit by the use of production-level 0. 5 µm GaAs MESFETs. The fabricated decision circuit achieves a data input sensitivity of 43 mVp-p and a phase margin of 240 both at 10-Gbit/s: a 230 mVp-p smaller input sensitivity and a 35 larger phase margin than those of conventional non-peaking inductor types.

This paper describes, for the first time, the circuit design considerations and measurements of core building blocks that support a 1.9-GHz-band (Band I) BiFET MMIC three-power-mode power amplifier (PA) for WCDMA handset applications. The blocks are a reference voltage (Vref) generator, a control logic circuit, and ESD protection circuits. Our proposed Vref-generator, based on a current-mirror topology, can successfully suppress Vref variation against threshold voltage (Vth) dispersion in the FET as well as current gain dispersion in the HBT. On-wafer measurements over several wafer lots show that the standard deviation of Vref is as small as 18 mV over a Vth dispersion range from -0.6 V to -1.0 V. As a result, the measured quiescent current dispersion in the HPM is also suppressed to less than 5.4 mA, despite the fact that the average quiescent current is relatively high, at 81.3 mA. Several simulations reveal that small decoupling capacitances of approximately 1 pF added to the gate control lines of RF switch FETs ensure stable operation of the control logic even if an undesired RF coupling is present between an RF signal path and the gate lines. An empirical and useful design approach for ESD protection using HBT base-collector diodes allows easy and precise estimation of the HBM ESD robustness. With the above building blocks, a 3 mm × 3 mm PA was designed and fabricated by an in-house BiFET process. Measurements conducted under the conditions of a 3.4-V supply voltage and a 1.95-GHz WCDMA modulated signal are as follows. The PA delivers a 28.3-dBm output power (Pout), a 28.2-dB power gain (Gp), and 40% PAE while restricting the ACLR1 to less than -42 dBc in the HPM. In the MPM, 17.4 dBm of Pout, 15.9 dB of Gp, and 25.3% of PAE are obtained, while in the LPM, the PA delivers 7 dBm of Pout, 11.7 dB of Gp, and 13.9% of PAE. The HBM ESD robustness is 2 kV.

This paper describes the design and measurements of two-gain-mode MMIC power amplifier modules (PAMs) for Band 1 and Band 5 WCDMA data communications. The PAMs are based on the two-stage single-chain amplifier topology with an L-shaped FET step attenuator (ATT) placed at the interstage, featuring not only high-efficiency operation but also both a small phase discontinuity and a small input return loss variation between the two gain modes: a high-gain mode (0-dB thru state for the ATT) and a low-gain mode (14-dB attenuation state for the ATT). The PAMs are assembled on a 3 mm × 3 mm FR-4 laminate together with several surface mount devices, and a high-directivity, 20-dB bilayer-type directional coupler is integrated on the laminate for accurate forward-power monitoring even under a 2.5:1-VSWR load mismatching condition. To validate the design and analysis for the PAMs using the L-shaped ATT, two PAM products — a Band 1 PAM and a Band 5 PAM — were fabricated using our in-house GaAs-BiFET process. The main RF measurements under the condition of a WCDMA (R99) modulated signal and a 3.4-V supply voltage are as follows. The Band 1 PAM can deliver a power-added efficiency (PAE) as high as 46% at an output power (Pout) of 28.25 dBm while maintaining a ±5-MHz-offset adjacent channel power ratio (ACLR1) of approximately -40 dBc or less and a small phase discontinuity of less than 5°. The Band 5 PAM can also deliver a high PAE of 46% at the same Pout and ACLR1 levels with small phase discontinuity of less than 4°. This small discontinuity is due to the phase-shift compensation capacitance embedded in the ATT. The measured input return loss is well maintained at better than 10 dB at the two modes. In addition, careful coupler design achieves a small detection error of less than 0.5 dB even under a 2.5:1-VSWR load mismatching condition.

We have demonstrated the single-chip RF front-end GaAs MMIC for the Japanese Personal Handy-phone System. It has a high efficiency HPA, a T/R switch, a LNA and a low-distortion down converter mixer. The IC employs a negative voltage generator for use of single voltage DC power supply. The HPA provides an output power of 21.5 dBm, with an ACPR of 55 dBc and an efficiency of 35%. The LNA has a noise figure of 1.6 dB and a gain of 14 dB with current of 2.3 mA. The newly developed active cascode FET mixer has a high IIP3 of 1 dBm with a high conversion gain of 10 dB and low consumption current of 2.3 mA. The IC is characterized by high performance for RF front-end of PHS handheld terminals. The IC is available in a 7.0 mm6.4 mm1.1 mm plastic package.

This paper describes 0.8-/1.5-GHz-band GaAs-HBT power amplifier modules with a newly designed analog bias control scheme. This scheme has two features. One is to achieve approximately linear quiescent current control using not a BiFET process but only the usual HBT process. The other is to help improve linearity under reduced supply voltage and lower quiescent current operation. The following two key techniques are incorporated into the bias scheme. The first is to employ two different kinds of bias circuits: emitter follower bias and current injection bias. The second is the unique current injection bias block, based on the successful combination of an input buffer with an emitter resistance load and a current mirror. These techniques allow quiescent current control that is almost proportional to an externally applied analog control voltage. To confirm the effectiveness of the scheme, 0.8-GHz-band and 1.5-GHz-band power amplifier modules were designed and fabricated using the usual HBT process. Measurements conducted under the conditions of a 3.4V supply voltage and an HSDPA WCDMA modulated signal are as follows. The 0.8-GHz-band amplifier can deliver a 28-dBm output power (Pout), a 28.4-dB power gain (Gp), and 42% PAE while restricting the ACLR to less than -40dBc. For the 1.5-GHz-band amplifier, 28dBm of Pout, 29dB of Gp, and 41% of PAE are obtained with the same ACLR levels. The measurements also confirm that the quiescent current for the second stage in the amplifiers is approximately linearly changed from 14mA to 58mA over a control voltage ranging from 1.1V to 2.2V. In addition, our measured DG.09-based current dissipation with both supply voltage and analog bias controls is as low as 16.9mA, showing that the analog bias control scheme enables an average current reduction of more than 20%, as compared to a conventional supply voltage and two-step quiescent current control.

This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/D-As) suitable for 2.4-GHz and 5.2-GHz short-range wireless applications. The ICs are fabricated in a 0.18 µm bulk CMOS which has no extra processing steps for enhancing the RF performance. The successful use of the current-reuse topology and interdigitated capacitors (IDCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in the bulk CMOS leading to large RF substrate and conductor losses. The main measurement results of the two LN/D-As are as follows: a 3.8-dB noise figure (NF) and a 10.1-dB gain under the conditions of 1.8 V and 6 mA, a 3.4-dBm 1-dB gain compressed output power (P1dB) for a 2.4-V voltage supply and a 13-mA operating current for the 2.4-GHz LN/D-A, and a 4.9-dB NF and an 11.1-dB gain with a 1.8 V and 10 mA supply condition, a 2.3-dBm P1dB at 2.4 V and 16 mA for the 5.2-GHz LN/D-A. Both MMICs are suited for low-noise amplifiers and driver amplifiers in 2.4-GHz and 5.2-GHz low-cost, low-power wireless systems such as Bluetooth and hiperLAN.

A microwave waveform measurement system below 18 GHz was developed and verified with a conventional RF measurement. The current and voltage RF waveforms of AlGaAs HBTs at the fundamental frequency of 1 GHz were directly measured with the system. A new direct method of sweeping and measuring dynamic RF load lines is proposed to measure the operating limits of the device. The maximum operating region was experimentally investigated with this method. The limits with a small input power are found to come from thermal runaway and the avalanche breakdown of the device. With a large input power, the HBT was found to operate beyond the DC limit of thermal runaway. The base ballasting resistance was also found to enhance large signal operating limits beyond those expected from the conventional DC theory.