We have demonstrated the single-chip RF front-end GaAs MMIC for the Japanese Personal Handy-phone System. It has a high efficiency HPA, a T/R switch, a LNA and a low-distortion down converter mixer. The IC employs a negative voltage generator for use of single voltage DC power supply. The HPA provides an output power of 21.5 dBm, with an ACPR of 55 dBc and an efficiency of 35%. The LNA has a noise figure of 1.6 dB and a gain of 14 dB with current of 2.3 mA. The newly developed active cascode FET mixer has a high IIP3 of 1 dBm with a high conversion gain of 10 dB and low consumption current of 2.3 mA. The IC is characterized by high performance for RF front-end of PHS handheld terminals. The IC is available in a 7.0 mm6.4 mm1.1 mm plastic package.

A high efficiency feedforward power amplifier (FFPA) with a series diode linearizer for cellular base stations is presented. In order to achieve the highest overall efficiency of an FFPA, an improved pre-distortion diode linearizer has been used and the bias condition of the main amplifier has been optimized. The optimum bias condition has been derived from the overall efficiency analysis of the FFPA with a pre-distortion linearizer. From measured overall performances of the FFPA, efficiency enhancement of the series diode linearizer has been verified. The developed FFPA achieved the efficiency of 10% and output power of 45.6 dBm at 10 MHz offset Adjacent Channel leakage Power Ratio (ACPR) -50 dBc under Wide-band Code-Division Multiple-Access (W-CDMA) modulated 2 carriers signal. This design method can be also used to optimize the source and load impedances condition of the main amplifier FET.

A direct calculation method of efficiency and power of FETs from d.c. characteristics determined by knee and breakdown voltages is proposed to make clear the requirements for knee and breakdown voltages of FETs under low-voltage operation of power amplifiers. It is shown from the calculation that the breakdown voltage has a greater effect on power and efficiency than the knee voltage and has to be three or more times of the operating voltage in order not to degrade efficiency under class-AB operation. A 3.3 V UHF-band 3-stage high efficiency and high power monolithic amplifier has been developed with the use of power FETs satisfying the requirements for knee and breakdown voltages under low-voltage operation. A power-added efficiency of 57.3% and a saturated output power of 31.8 dBm have been achieved for a drain voltage of 3.3 V in UHF-band. The direct calculation method of efficiency and power from d.c. characteristics, which can provide the required knee or breakdown voltage for a given efficiency, power, or bias conditions, is considered to be useful for developing power devices with various requirements for efficiency, power, and bias conditions.

This paper proposes a new distortion analysis method for frequency-dependent FET amplifiers, which uses a novel Frequency-Dependent Complex Power Series (FDCPS) model. This model consists of a frequency-independent nonlinear amplifier represented by an odd-order complex power series and frequency-dependent input and output filters. The in-band frequency characteristics of the saturation region are represented by the frequency-dependent output filter, while the in-band frequency characteristics of the linear region are represented by the frequency-dependent input and output filters. In this method, the time-domain analysis is carried out to calculate the frequency-independent nonlinear amplifier characteristics, and the frequency-domain analysis is applied to calculate the frequency-dependent input and output filter characteristics. The third-order intermodulation (IM3) calculated by this method for a GaAs MESFET amplifier is in good agreement with the numerical results obtained by the Harmonic Balance (HB) method. Moreover, the IM3 calculated by this method also agrees well with the measured data for an L-band 3-stage GaAs MESFET amplifier. It is shown that this method is effective for calculating frequency-dependent distortion of a nonlinear amplifier with broadband modulation signals.

An efficient large-signal modeling method of FET using load-line analysis is proposed, and it is applied to non-linear characterization of FET. In this method, instantaneous drain-source voltage Vds(t) and drain-source current Ids(t) waveforms are determined by load-line analysis while non-linear parameters in a large-signal equivalent circuit of FET are defined as the average values over one period corresponding to instantaneous Vds(t) and Ids(t). Output power (Pout), power added efficiency (ηadd), and phase deviation calculated by using such an equivalent circuit of FET agree well with the measured results at 933.5 MHz. Phase deviation mechanism is explained based on the large-signal equivalent circuit of FET, and it is shown how non-linear parameters, such as trans-conductance (gm), drain-source resistance (Rds), gate-source capacitance (Cgs), and gate leak resistance (Rig) contribute to positive or negative phase deviations. The difference between small-signal and large-signal S-parameters (S11, S12, S21, S22) is also discussed. The proposed large-signal modeling method is considered to be useful for the design of high power, high efficiency, and low distortion amplifiers as well as the investigation of the behavior of FET in large-signal operating conditions.

An 18 GHz-band Microwave Monolithic Integrated Circuit (MMIC) diode linearizer using a parallel capacitor with a bias feed resistance is presented. The newly employed parallel capacitor is able to control gain and phase deviations of the linearizer. This implies that the gain deviation of the linearizer can be controlled without changing the phase deviation. The presented linearizer can compensate the distortion of an amplifier sufficiently. The operation principle of the linearizer with the parallel capacitor is investigated. It is clarified that the gain deviation can be adjusted without changing the phase deviation by using the parallel capacitor. Two variable gain buffer amplifiers and the core part of the linearizer which consists of a diode, a bias feed resistor, and a capacitor are fabricated on the MMIC chip. The amplifiers cancel the frequency dependence of the core part of the linearizer to improve bandwidth of the MMIC. Further, the amplifiers contribute to earn low reflection and compensate insertion loss of the linearizer. The MMIC chip is size of 2.5 mm 1 mm. The linearizer has demonstrated improvement of 3rd Inter-Modulation Distortion (IMD3) of 12 dB at 18 GHz and improvement of more than 6 dB between 17.8 GHz and 18.6 GHz.

A novel design method for wideband low-noise multi-stage amplifiers is presented. It utilizes a RL-SFC (esistive oaded eries eedback ircuit) comprised of a series feedback circuit with additional lossy match stubs to achieve low noise figure, low VSWRs, flat gain, and high stability simultaneously. In addition, each stage amplifier employs a different approach for designing the RL-SFC to achieve the best compromise between noise figure, VSWR, gain, and stability as a multi-stage amplifier. With the use of this novel design method, the 3-stage amplifier has demonstrated the state-of-the-art wideband low-noise performance of 2.3 dB over 6 to 18 GHz.

This paper describes the design, fabrication, and performance of a GaAs FET linearizer with a large source inductance, focusing mainly on (a) a mechanism of positive gain and negative phase deviations for input power, (b) stability considerations, and (c) a dependence on load impedance. In addition, in an application to the linearized amplifier, it is shown that an improvement can be achieved for adjacent channel leakage power (ACP) and third order intermodulation distortion (IM3) with the use of the linearizer.

This paper proposes a design method of a Doherty amplifier, which can determine the most efficient backed-off point of the amplifier by adjusting a load modulation parameter. The parameter is defined through the design of output transmission line of a carrier and a peak amplifier using a virtual open stub technique. This paper describes the design results using the technique to optimize efficiency of a Doherty amplifier for an orthogonal frequency division multiplexing (OFDM) signal, and parameter adjustment for a linearized Doherty amplifier using an adaptive digital predistortion (ADPD). Applying this method, the developed 250 W ADPD Doherty amplifier has achieved drain efficiency of 43.4% and intermodulation (IM) distortion of -48.3 dBc with output power of 44.1 dBm (10.1 dB output backed-off) at 563 MHz using an OFDM signal for integrated services digital broadcasting-terrestrial (ISDB-T).

A matched load for post-wall waveguide (SIW; Substrate Integrated Waveguide) is presented. It consists of an electrically-shorted post-wall waveguide and a rectangular thin-film resistor sheet on the surface of the waveguide, resulting in a quite compact structure without three-dimensional bulky absorber as in conventional waveguide matched loads. A fabricated X-band matched load has achieved less than -20 dB reflection in more than 20% relative bandwidth.

A new GaAs negative voltage generator suitable for biasing a GaAs MESFET power amplifier has been successfully developed and applied to a 1.9-GHz single-chip transmit/receive (T/R)-MMIC front-end including a power amplifier, a T/R-switch, and so on. To meet various requirements necessary for integration with a power amplifier, four new circuit techniques are introduced into this generator: (1)complementary charge pump operation to suppress spurious outputs. (2)an SCFL-to-DCFL cross-coupled level shifter to ensure a wide operation voltage range, (3)a level control circuit to reduce output voltage deviation caused by output current, and (4)interface and layout designs to achieve sufficient isolation between the power amplifier and the generator. The generator was incorporated into the MMIC front-end, and it was tested with a 30-lead shrink small outline package. With 20-to-500-MHz external input signals of more than -15 dBm, the generator produces negative voltages from -1.0 to -2.6 V for a wide range of suppiy voltages from 1.6 to 4.5 V. The current consumption is as low as 3.2 mA at 3 V. When a 22-dBm output is delivered through the power amplifier biased by the generator, low spurious outputs below -70 dBc are achieved. and gate-bias voltage deviations are suppressed to within 0.06 V even when a gate current of -140 µA flows through the amplifier. The generator also enables high speed operation of charge time below 200 ns, which is effective in TDMA systems such as digital cordless telephone systems. In layout design, electromagnetic simulation was utilized for estimating sufficient isolation between circuits in the MMIC. This negative voltage generator and its application techniques will enable GaAs high-density integration devices as well as single voltage operation of a GaAs MESFET power amplifier.

Weight divided adaptive control method for a microwave FeedForward Power Amplifier (FFPA) is presented. In this adaptive controller, an output signal of a power amplifier is used as reference signal. Additionally, reference signal is divided by the weight of adaptive filter, so that characteristics of the power amplifier, such as temperature dependence, do not have influence on the convergence performances. The proposed adaptive algorithm and the convergence condition are derived analytically and we clarify that the proposed weight divided adaptive algorithm is more stable than the conventional Normalized Least Mean Square (NLMS) algorithm. Then, the convergence condition considering phase calibration error is discussed. The effectiveness of the proposed algorithm are also verified by the nonlinear simulations of the FFPA having AM-AM and AM-PM nonlinearity of GaAsFET.

High-power T/R switch with GaN HEMT technology is successfully developed, and the design theory is formulated. The proposed switch employs an asymmetric series-shunt/shunt configuration. Because the power handling capability of the proposed switch is mainly dependent of the breakdown voltage of FETs, the proposed circuit can make full use of the characteristics of the GaN HEMT technology. The switch has a high degree of freedom for the FET gate widths, so the low insertion loss can be obtained while keeping high-power performances. To verify this methodology, T/R switch has been fabricated in X-band. The fabricated switch has demonstrated an insertion loss of 1.8 dB in Rx-mode, 1.2 dB in Tx-mode and power handling capability of 20 W in 53% bandwidth.