This paper proposes a design method of a Doherty amplifier, which can determine the most efficient backed-off point of the amplifier by adjusting a load modulation parameter. The parameter is defined through the design of output transmission line of a carrier and a peak amplifier using a virtual open stub technique. This paper describes the design results using the technique to optimize efficiency of a Doherty amplifier for an orthogonal frequency division multiplexing (OFDM) signal, and parameter adjustment for a linearized Doherty amplifier using an adaptive digital predistortion (ADPD). Applying this method, the developed 250 W ADPD Doherty amplifier has achieved drain efficiency of 43.4% and intermodulation (IM) distortion of -48.3 dBc with output power of 44.1 dBm (10.1 dB output backed-off) at 563 MHz using an OFDM signal for integrated services digital broadcasting-terrestrial (ISDB-T).

Weight divided adaptive control method for a microwave FeedForward Power Amplifier (FFPA) is presented. In this adaptive controller, an output signal of a power amplifier is used as reference signal. Additionally, reference signal is divided by the weight of adaptive filter, so that characteristics of the power amplifier, such as temperature dependence, do not have influence on the convergence performances. The proposed adaptive algorithm and the convergence condition are derived analytically and we clarify that the proposed weight divided adaptive algorithm is more stable than the conventional Normalized Least Mean Square (NLMS) algorithm. Then, the convergence condition considering phase calibration error is discussed. The effectiveness of the proposed algorithm are also verified by the nonlinear simulations of the FFPA having AM-AM and AM-PM nonlinearity of GaAsFET.

This paper describes, for the first time, the circuit design considerations and measurements of core building blocks that support a 1.9-GHz-band (Band I) BiFET MMIC three-power-mode power amplifier (PA) for WCDMA handset applications. The blocks are a reference voltage (Vref) generator, a control logic circuit, and ESD protection circuits. Our proposed Vref-generator, based on a current-mirror topology, can successfully suppress Vref variation against threshold voltage (Vth) dispersion in the FET as well as current gain dispersion in the HBT. On-wafer measurements over several wafer lots show that the standard deviation of Vref is as small as 18 mV over a Vth dispersion range from -0.6 V to -1.0 V. As a result, the measured quiescent current dispersion in the HPM is also suppressed to less than 5.4 mA, despite the fact that the average quiescent current is relatively high, at 81.3 mA. Several simulations reveal that small decoupling capacitances of approximately 1 pF added to the gate control lines of RF switch FETs ensure stable operation of the control logic even if an undesired RF coupling is present between an RF signal path and the gate lines. An empirical and useful design approach for ESD protection using HBT base-collector diodes allows easy and precise estimation of the HBM ESD robustness. With the above building blocks, a 3 mm × 3 mm PA was designed and fabricated by an in-house BiFET process. Measurements conducted under the conditions of a 3.4-V supply voltage and a 1.95-GHz WCDMA modulated signal are as follows. The PA delivers a 28.3-dBm output power (Pout), a 28.2-dB power gain (Gp), and 40% PAE while restricting the ACLR1 to less than -42 dBc in the HPM. In the MPM, 17.4 dBm of Pout, 15.9 dB of Gp, and 25.3% of PAE are obtained, while in the LPM, the PA delivers 7 dBm of Pout, 11.7 dB of Gp, and 13.9% of PAE. The HBM ESD robustness is 2 kV.

We have demonstrated the single-chip RF front-end GaAs MMIC for the Japanese Personal Handy-phone System. It has a high efficiency HPA, a T/R switch, a LNA and a low-distortion down converter mixer. The IC employs a negative voltage generator for use of single voltage DC power supply. The HPA provides an output power of 21.5 dBm, with an ACPR of 55 dBc and an efficiency of 35%. The LNA has a noise figure of 1.6 dB and a gain of 14 dB with current of 2.3 mA. The newly developed active cascode FET mixer has a high IIP3 of 1 dBm with a high conversion gain of 10 dB and low consumption current of 2.3 mA. The IC is characterized by high performance for RF front-end of PHS handheld terminals. The IC is available in a 7.0 mm6.4 mm1.1 mm plastic package.

A high efficiency feedforward power amplifier (FFPA) with a series diode linearizer for cellular base stations is presented. In order to achieve the highest overall efficiency of an FFPA, an improved pre-distortion diode linearizer has been used and the bias condition of the main amplifier has been optimized. The optimum bias condition has been derived from the overall efficiency analysis of the FFPA with a pre-distortion linearizer. From measured overall performances of the FFPA, efficiency enhancement of the series diode linearizer has been verified. The developed FFPA achieved the efficiency of 10% and output power of 45.6 dBm at 10 MHz offset Adjacent Channel leakage Power Ratio (ACPR) -50 dBc under Wide-band Code-Division Multiple-Access (W-CDMA) modulated 2 carriers signal. This design method can be also used to optimize the source and load impedances condition of the main amplifier FET.

This paper proposes a new distortion analysis method for frequency-dependent FET amplifiers, which uses a novel Frequency-Dependent Complex Power Series (FDCPS) model. This model consists of a frequency-independent nonlinear amplifier represented by an odd-order complex power series and frequency-dependent input and output filters. The in-band frequency characteristics of the saturation region are represented by the frequency-dependent output filter, while the in-band frequency characteristics of the linear region are represented by the frequency-dependent input and output filters. In this method, the time-domain analysis is carried out to calculate the frequency-independent nonlinear amplifier characteristics, and the frequency-domain analysis is applied to calculate the frequency-dependent input and output filter characteristics. The third-order intermodulation (IM3) calculated by this method for a GaAs MESFET amplifier is in good agreement with the numerical results obtained by the Harmonic Balance (HB) method. Moreover, the IM3 calculated by this method also agrees well with the measured data for an L-band 3-stage GaAs MESFET amplifier. It is shown that this method is effective for calculating frequency-dependent distortion of a nonlinear amplifier with broadband modulation signals.

This paper presents a digital predistorter with a wideband memory effect compensator for a Doherty power amplifier (PA). A simple memory-predistortion model, which consists of a look-up-table (LUT) and an adaptive filter equalizing memory effects, and a new memory effect estimation algorithm using a direct-learning architecture are proposed. The proposed estimation algorithm has an advantage that a transfer function of a feedback circuit does not affect the learning process. The predistorter is implemented in a field programmable gate array (FPGA) and a digital signal processor (DSP). The transmitter has achieved distortion level of -50.8 dBr at signal bandwidth away from the carrier, and PA module efficiency of 24% with output power of 43 dBm at 2595 MHz under a 20 MHz-bandwidth orthogonal frequency division multiplexing (OFDM) signal using laterally diffused metal oxide semiconductor (LDMOS) FETs.