A direct calculation method of efficiency and power of FETs from d.c. characteristics determined by knee and breakdown voltages is proposed to make clear the requirements for knee and breakdown voltages of FETs under low-voltage operation of power amplifiers. It is shown from the calculation that the breakdown voltage has a greater effect on power and efficiency than the knee voltage and has to be three or more times of the operating voltage in order not to degrade efficiency under class-AB operation. A 3.3 V UHF-band 3-stage high efficiency and high power monolithic amplifier has been developed with the use of power FETs satisfying the requirements for knee and breakdown voltages under low-voltage operation. A power-added efficiency of 57.3% and a saturated output power of 31.8 dBm have been achieved for a drain voltage of 3.3 V in UHF-band. The direct calculation method of efficiency and power from d.c. characteristics, which can provide the required knee or breakdown voltage for a given efficiency, power, or bias conditions, is considered to be useful for developing power devices with various requirements for efficiency, power, and bias conditions.

This paper treats the problem of realizing high speed 2-D denominator separable digital filters. Partitioning a 2-D data plane into square blocks, filtering proceeds block by block sequentially. A fast intra-block parallel processing method was developed using block state space realization, which allows simultaneous computation of all the next block states and the outputs of one block. As the block state matrix of the filter has high sparsity, the rows and columns are interchanged respectively to reduce the matrix size. The filter is implemented by a multiprocessor system, where for each matrix's row one processor is assigned to perform the row-column vector multiplication. All processors wirk in synchronized fashion. Number of processors of this implementation are equal to the number of rows of the reduced state matrix and throughput is raised with block lengths.