A new broadband buffer circuit technique and its analytical design method are proposed for a high-speed decision circuit featuring both a higher input sensitivity and a larger phase margin. The buffer circuit characteristics are significantly improved by employing a series peaking source follower (SPSF), where a peaking inductor is inserted between the first and second source follower stages. Optimization of the peaking inductance successfully enhances the 3-dB bandwidth of the data-input buffer and the clock buffer by 7 GHz for both, over conventional double-stage source follower SCFL buffers. The proposed circuit technique and design method are applied to a 10-Gbit/s decision circuit by the use of production-level 0. 5 µm GaAs MESFETs. The fabricated decision circuit achieves a data input sensitivity of 43 mVp-p and a phase margin of 240 both at 10-Gbit/s: a 230 mVp-p smaller input sensitivity and a 35 larger phase margin than those of conventional non-peaking inductor types.

A refection type and loaded-line type phase shifter switching multi phase-states has been described. This novel phase shifter circuit is constructed by adding switching FETs to a conventional 2-phase-state phase shifter. A conventional 3 bit phase shifter can be replaced by this type of phase shifter. The total chip size is reduced to 2/3. This paper reports on the design, fabrication, and performance of the novel reflection-type and loaded-line-type phase shifter MMICs.

This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.