IEICE TRANSACTIONS on Electronics
A Novel Layout Optimization Technique for Miniaturization and Accurate Design of MMICs
Summary :
This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E82-C No.11 pp.1960-1967
- Publication Date
- 1999/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century)
- Category
- Low Power-Consumption RF ICs
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Shin CHAKI, Yoshinobu SASAKI, Naoto ANDOH, Yasuharu NAKAJIMA, Kazuo NISHITANI, "A Novel Layout Optimization Technique for Miniaturization and Accurate Design of MMICs" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 11, pp. 1960-1967, November 1999, doi: .
Abstract: This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_11_1960/_p
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@ARTICLE{e82-c_11_1960,
author={Shin CHAKI, Yoshinobu SASAKI, Naoto ANDOH, Yasuharu NAKAJIMA, Kazuo NISHITANI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Layout Optimization Technique for Miniaturization and Accurate Design of MMICs},
year={1999},
volume={E82-C},
number={11},
pages={1960-1967},
abstract={This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.},
keywords={},
doi={},
ISSN={},
month={November},}
Copy
TY - JOUR
TI - A Novel Layout Optimization Technique for Miniaturization and Accurate Design of MMICs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1960
EP - 1967
AU - Shin CHAKI
AU - Yoshinobu SASAKI
AU - Naoto ANDOH
AU - Yasuharu NAKAJIMA
AU - Kazuo NISHITANI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1999
AB - This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.
ER -
English
