The equivalent circuit of ion projection-driven EPD is derived from the property of the ion current, and its adequateness is shown by the agreement of the voltage applied to the suspension calculated from the equivalent circuit and the property of the contrast ratio. Then, the improvement of the contrast ratio of the new suspension prepared on the basis of the idea by considering the equivalent circuit is described.

In this paper we describe the pipeline design and enhanced hardware for fast message handling in a RICA-1 processor, a processing element (PE) in the RWC-1 multiprocessor. The RWC-1 is based on the reduced inter-processor communication architecture (RICA), in which communications are combined with computation in the processor pipeline. The pipeline is enhanced with hardware mechanisms to support fine-grain parallel execution. The data paths of the RICA-1 super-scalar processor are commonly used for communication as well as instruction execution to minimize its implementation cost. A 128-PE system has been built on January 1998, and it is currently used for hardware debugging, software development and performance evaluation.

A refection type and loaded-line type phase shifter switching multi phase-states has been described. This novel phase shifter circuit is constructed by adding switching FETs to a conventional 2-phase-state phase shifter. A conventional 3 bit phase shifter can be replaced by this type of phase shifter. The total chip size is reduced to 2/3. This paper reports on the design, fabrication, and performance of the novel reflection-type and loaded-line-type phase shifter MMICs.

Air-bridge metal interconnection technology is used for upper level power supply line interconnections in GaAs LSI's to reduce the signal propagation delay time. This technology reduces both parasitic capacitance between the signal line and the power supply line, and propagation delay in the signal line to about 10% and about 50%, respectively, compared to conventional 3-level interconnections without air-bridges. Under standard load conditions (FI=FO=2, length of load line=2 mm), the air-bridge technique leads to gate propagation delays which are about 60% of those in conventional interconnections. We fabricated 2.1-k gate Gate Arrays and 4-kb SRAM's using the air-bridge structure to interconnect power supply lines. For a Gate Array with 0.7 µm gate Buried P-layer Lightly Doped Drain (BPLDD) FET's, the typical gate propagation delay under standard load conditions was about 110 ps with a dissipation power of 1.4 mW/gate. SRAM's with 05 µm gate BPLDD's had typical access time (tacc) of 1.5 ns with a dissipation power of 700 mW/chip.

This paper discusses a massively parallel interconnection scheme for multithreaded architecture and introduces a new class of direct interconnection networks called the hierarchical Multidimensional Directed Cycles Ensemble (hMDCE). Its suitability for massively parallel systems is discussed. The network is evolved from the Multidimensional Directed Cycles Ensemble (MDCE) network, where each node is substituted by lower-level sub-networks. The new network addresses some serious problems caused by the increasing scale of parallel systems, such as longer latency, limited throughput and high implementation cost. This paper first introduces the MDCE network and then presents and examines in detail the hierarchical MDCE network. Bisection bandwidth of hMDCE is considerably reduced from its ancestor MDCE and the network performs significantly higher throughput and lower latency under some practical implementation constraints. The gate count and delay time of the compiled circuit for the routing function are insignificant. These results reveal that the hMDCE network is an important candidate for massively parallel systems interconnection.