A new broadband buffer circuit technique and its analytical design method are proposed for a high-speed decision circuit featuring both a higher input sensitivity and a larger phase margin. The buffer circuit characteristics are significantly improved by employing a series peaking source follower (SPSF), where a peaking inductor is inserted between the first and second source follower stages. Optimization of the peaking inductance successfully enhances the 3-dB bandwidth of the data-input buffer and the clock buffer by 7 GHz for both, over conventional double-stage source follower SCFL buffers. The proposed circuit technique and design method are applied to a 10-Gbit/s decision circuit by the use of production-level 0. 5 µm GaAs MESFETs. The fabricated decision circuit achieves a data input sensitivity of 43 mVp-p and a phase margin of 240 both at 10-Gbit/s: a 230 mVp-p smaller input sensitivity and a 35 larger phase margin than those of conventional non-peaking inductor types.

10G-EPON systems have attracted a great deal of attention as a way of exceeding to realize over 10 Gb/s for optical subscriber networking. Rapid burst-mode transmitting/receiving techniques are the key technologies enabling the burst-mode upstream transmission of 10G-EPON systems. In this paper, we have developed a OLT burst-mode 3R receiver incorporating a burst-mode AGC optical receiver and an 82.5 GS/s over-sampling burst-mode CDR and a ONU burst-mode transmitter with high launch power DFB-LD of 1.27 µm wavelength to fully compliant with IEEE802.3av 10G-EPON PR30 standards. The transmitting characteristics of a fast LD turn-on/off time of less than 6ns and a high launch power of more than +8.0 dBm, and the receiving characteristics of receiver sensitivity of -30.1 dBm and the upstream power budget of 38.1 dB are successfully achieved.

We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.