A new GaAs negative voltage generator suitable for biasing a GaAs MESFET power amplifier has been successfully developed and applied to a 1.9-GHz single-chip transmit/receive (T/R)-MMIC front-end including a power amplifier, a T/R-switch, and so on. To meet various requirements necessary for integration with a power amplifier, four new circuit techniques are introduced into this generator: (1)complementary charge pump operation to suppress spurious outputs. (2)an SCFL-to-DCFL cross-coupled level shifter to ensure a wide operation voltage range, (3)a level control circuit to reduce output voltage deviation caused by output current, and (4)interface and layout designs to achieve sufficient isolation between the power amplifier and the generator. The generator was incorporated into the MMIC front-end, and it was tested with a 30-lead shrink small outline package. With 20-to-500-MHz external input signals of more than -15 dBm, the generator produces negative voltages from -1.0 to -2.6 V for a wide range of suppiy voltages from 1.6 to 4.5 V. The current consumption is as low as 3.2 mA at 3 V. When a 22-dBm output is delivered through the power amplifier biased by the generator, low spurious outputs below -70 dBc are achieved. and gate-bias voltage deviations are suppressed to within 0.06 V even when a gate current of -140 µA flows through the amplifier. The generator also enables high speed operation of charge time below 200 ns, which is effective in TDMA systems such as digital cordless telephone systems. In layout design, electromagnetic simulation was utilized for estimating sufficient isolation between circuits in the MMIC. This negative voltage generator and its application techniques will enable GaAs high-density integration devices as well as single voltage operation of a GaAs MESFET power amplifier.

A single-chip GaAs Transmit/Receive (T/R)-MMIC front-end has been developed which is applicable to 1. 9-GHz personal communication terminals such as digital cordless phones. This chip is fabricated using a planar self-aligned gate FET useful for low-cost and high-volume production. The chip integrates RF front-end analog circuits a power amplifier, a T/R-switch, and a low-noise amplifier. Additionally integrated are a newly developed voltage-doubler negative-voltage generator (VDNVG) and a control logic circuit to control transmit and receive functions, enabling both a single-voltage operation and an enhanced power handling capability of the switch, even under a single low-voltage supply condition of 2 V. The power amplifier incorporated onto the chip is capable of delivering a 21 dBm output power at a 39% efficiency, and a 30 dB associated gain with a 2 V single power supply in the transmit mode. The gain and efficiency are higher than those of the previously reported amplifier operating with a 2 V single power supply. The VDNVG produces a step-up voltage of 2. 9 V as well as a negative voltage of -1. 8 V from a 2 V power supply, operating with a charge time of less than 0. 25 µs. The control logic circuit on the chip has a newly designed interface circuit utilizing the step-up voltage and negative voltage, thereby enabling the chip to handle high power outputs over 24 dBm with a low operating voltage of 2 V. In the receive mode, a 1. 7 dB noise figure and a 0. 6 dB insertion loss are achieved with a current dissipation of 3. 6 mA. The developed MMIC, which is the first reported 2 V single-voltage operation T/R-MMIC front-end, is expected to contribute to the size and weight reductions in personal communication terminals.

We have demonstrated the single-chip RF front-end GaAs MMIC for the Japanese Personal Handy-phone System. It has a high efficiency HPA, a T/R switch, a LNA and a low-distortion down converter mixer. The IC employs a negative voltage generator for use of single voltage DC power supply. The HPA provides an output power of 21.5 dBm, with an ACPR of 55 dBc and an efficiency of 35%. The LNA has a noise figure of 1.6 dB and a gain of 14 dB with current of 2.3 mA. The newly developed active cascode FET mixer has a high IIP3 of 1 dBm with a high conversion gain of 10 dB and low consumption current of 2.3 mA. The IC is characterized by high performance for RF front-end of PHS handheld terminals. The IC is available in a 7.0 mm6.4 mm1.1 mm plastic package.

A simulation tool for analyzing circuit characteristics of microstrip-type MIC (Microwave Integrated Circuit) passive elements is presented. The major part of this tool is the electromagnetic wave analysis based on the FD-TD (Finite-Difference Time-Domain) method combined with the mode expansion theory. Although the element structures which can be treated in this tool are limited to only less than ten fundamental structures in the present stage, its extension to the more versatile tool applicable to other various element types is rather straightforward and simple in principle. When using this tool, we first choose the element configuration to be calculated and give, on a panel, necessary parameter values related to calculation range and mesh division scheme. Given these values, the first step calculation starts to obtain the characteristic impedance, cross sectional field distribution of the propagating mode, etc. of the basic microstrip line. Field distributions around the element configulation are calculated next with the mode field oscillation being given. Through this process the field distributions on a closed rectangular parallelepiped surface enclosing the element configuration are stored in files, from which S parameter and radiated fields are calculated by invoking the reaction integral with propagation modes and radiation modes, respectively. The results obtained in these three steps can be expressed, at our discretion, as line drawings or two-dimensional density plots.

In many packet switched networks, packet sizes are basically 128 or 256 bytes, probably due to their adaptation to interactive communications with short delay requirement. However, in order to deal with message communications also, characterized as bulk, unidirectional and delay tolerable, the networks may be required to handle a larger packet size suitable for the message communications characteristics. This paper calls packet switching systems, which handle various sizes of packets, heterogeneous packet switching systems. Focusing on packet transfer cost in heterogeneous packet switching systems, this paper discusses an optimum packet size for message communications. For an optimum packet size, an approximate and analytical solution is obtained when packet header length is ignored. Moreover, strict and numerical calculation results under a general condition are also shown. It is shown that the approximation gives a smaller size than the strict solution. Further, the effect of cost reduction caused by an optimum packet size for message communications is evaluated. As a result, the cost in heterogeneous packet switching is confirmed to be reduced to about half, especially when message communications traffic is dominant.