A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

In many packet switched networks, packet sizes are basically 128 or 256 bytes, probably due to their adaptation to interactive communications with short delay requirement. However, in order to deal with message communications also, characterized as bulk, unidirectional and delay tolerable, the networks may be required to handle a larger packet size suitable for the message communications characteristics. This paper calls packet switching systems, which handle various sizes of packets, heterogeneous packet switching systems. Focusing on packet transfer cost in heterogeneous packet switching systems, this paper discusses an optimum packet size for message communications. For an optimum packet size, an approximate and analytical solution is obtained when packet header length is ignored. Moreover, strict and numerical calculation results under a general condition are also shown. It is shown that the approximation gives a smaller size than the strict solution. Further, the effect of cost reduction caused by an optimum packet size for message communications is evaluated. As a result, the cost in heterogeneous packet switching is confirmed to be reduced to about half, especially when message communications traffic is dominant.

The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2 4 GB/s at 4 macros. The process cost has been kept low by using VT-MOS circuit technology and taking advantage of a characteristic of dual-gate oxide process technology. A tRAC of 11.6 ns at 2.0 V is achieved using a 'pre-detect redundancy' circuit.

We propose a hardware-based packet forwarder for multi-gigabit IP backbone networks. The conventional Internet deploys routers as a key block, but its software-controlled architecture makes it hard to scale up the packet forwarders, especially for table-lookup processes. We propose introducing a pure connectionless (CL) switching approach with a hardware-based forwarder to construct the core part of a scalable IP multi-gigabit backbone. Compared to a software-based forwarder, the table-lookup time is reduced to 100 ns by using content-addressable memory. This hardware-based pipeline implementation easily achieves a maximum forwarding performance of up to 9. 6-Gbps, or 23 million packets per second, for applications ranging from traditional best-effort IP applications to newly emerging time-critical ones. We also consider additional processing when transferring IP packets to enhance best-effort quality. This is done using selective packet-level discarding, including early packet discard and its enhancement, to achieve minimum bandwidth guaranteed service at the packet level. We discuss the IP backbone scalability issue from the viewpoint of new IP-forwarder technologies, paying special attention to connection-oriented (CO) vs. CL switching and hardware vs. software implementation. A pure CL switching solution consisting of a CL server (CLS) and a CL client (CLC) is proposed to balance the hardware- and software-based CL transport functions. As a first step to this solution, a compact CLS has been developed. It supports 600-Mbps throughput and up to 9. 6-Gbps forwarding power using a modular architecture. It was evaluated in an ATM field trial using an experimental network. The results show the effectiveness of our approach to providing enhanced best effort services.

This paper describes an Embedded DRAM Hybrid Macro, which supports various memory specifications. The eDRAM module generator with Hybrid Macro provides more than 120,000 eDRAM configurations. This eDRAM includes a new architecture called Auto Signal Management (ASM) architecture, which automatically adjusts the timing of the control signals for various eDRAM configurations, and reduces the design Turn Around Time. An Enhanced-on-chip Tester performs the maximum 512b I/O pass/fail simultaneous judgments and the real time repair analysis. The eDRAM testing time is reduced to about 1/64 of the time required using the conventional technique. A test chip is fabricated using a 0.18 µm 4-metal embedded DRAM technology, which utilizes the triple-well, dual-Tox, and Co salicide process technologies. This chip achieves a wide voltage range operation of 1.2 V at 100 MHz to 1.8 V at 200 MHz.

This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. And fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-µm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3mm2 is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-hit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants(PDA's), personal computer systems, and embedded controller applications.