A low power 16 Mb embedded DRAM (eDRAM) macro is fabricated using 0.15 µm logic -based embedded DRAM process technology. A 0.5 µm2 CUB (apacitor nder it-line) DRAM cell is newly developed for this process. Novel start-up and dynamic fuse-data loading circuit are developed to realize easy customization of memory capacities with minimum area penalty. A new write-mask control circuit using write-gate sense-amplifier is adopted in order to apply column shift-redundancy circuit. Various low power technologies including unique "non-precharge read-data bus" method are applied. In the test-chip adopting new process-technology and three original circuit-design techniques, random column operation of 166 MHz and data retention power of 123 µW are demonstrated at 1.5 V power supply.

This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.

The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.