IEICE TRANSACTIONS on Electronics
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros
Summary :
The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.10 pp.2020-2027
- Publication Date
- 2005/10/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.10.2020
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Akira YAMAZAKI
Fukashi MORISHITA
Naoya WATANABE
Teruhiko AMANO
Masaru HARAGUCHI
Hideyuki NODA
Atsushi HACHISUKA
Katsumi DOSAKA
Kazutami ARIMOTO
Setsuo WAKE
Hideyuki OZAKI
Tsutomu YOSHIHARA
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Akira YAMAZAKI, Fukashi MORISHITA, Naoya WATANABE, Teruhiko AMANO, Masaru HARAGUCHI, Hideyuki NODA, Atsushi HACHISUKA, Katsumi DOSAKA, Kazutami ARIMOTO, Setsuo WAKE, Hideyuki OZAKI, Tsutomu YOSHIHARA, "A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 10, pp. 2020-2027, October 2005, doi: 10.1093/ietele/e88-c.10.2020.
Abstract: The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.10.2020/_p
Copy
@ARTICLE{e88-c_10_2020,
author={Akira YAMAZAKI, Fukashi MORISHITA, Naoya WATANABE, Teruhiko AMANO, Masaru HARAGUCHI, Hideyuki NODA, Atsushi HACHISUKA, Katsumi DOSAKA, Kazutami ARIMOTO, Setsuo WAKE, Hideyuki OZAKI, Tsutomu YOSHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros},
year={2005},
volume={E88-C},
number={10},
pages={2020-2027},
abstract={The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.},
keywords={},
doi={10.1093/ietele/e88-c.10.2020},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros
T2 - IEICE TRANSACTIONS on Electronics
SP - 2020
EP - 2027
AU - Akira YAMAZAKI
AU - Fukashi MORISHITA
AU - Naoya WATANABE
AU - Teruhiko AMANO
AU - Masaru HARAGUCHI
AU - Hideyuki NODA
AU - Atsushi HACHISUKA
AU - Katsumi DOSAKA
AU - Kazutami ARIMOTO
AU - Setsuo WAKE
AU - Hideyuki OZAKI
AU - Tsutomu YOSHIHARA
PY - 2005
DO - 10.1093/ietele/e88-c.10.2020
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2005
AB - The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-µm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.
ER -
English
